SNAA411 September   2024 CDCLVC1102 , CDCLVC1103 , CDCLVC1104 , CDCLVC1110 , CDCLVD1204 , LMK00301 , LMK00304 , LMK00306 , LMK00308 , LMK01801 , LMK04832 , LMK1C1102 , LMK1C1103 , LMK1C1104 , LMK1C1106 , LMK1C1108 , LMK1D1204 , LMK1D1208 , LMX2485 , LMX2491 , LMX2572 , LMX2592 , LMX2594 , LMX2595 , LMX2820

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Generic Clock Tree
  5. 2Sine Wave Slew Rate Requirement
  6. 3Current Approach vs Clock Buffer
  7. 4Clock Buffer Implementation
    1. 4.1 Clock Buffer Common Input Stages
    2. 4.2 Choosing Between Internal or External DC Bias
    3. 4.3 Single Ended or LVCMOS Signal
    4. 4.4 Differential Inputs
  8. 5Performance Improvements, Results With Clock Buffer
    1. 5.1 FSWP Phase Noise Analyzer Measurements Case
    2. 5.2 TI LMX2820 Noise Improvements With Sine to Square Wave Clock Buffer
      1. 5.2.1 LMX2820 Phase Noise and RMS Jitter Results Summary
  9. 6Sine to Square Wave Clock Buffer Comparison
    1. 6.1 LMK1C110x Additive Noise vs Others
  10. 7Summary
  11. 8References

3 Current Approach vs Clock Buffer

Current approaches to solve slew rate sensitivity problem use additional circuitry is input of clock devices that takes additional space on the board. The overall system becomes costly and dependency of multiple discrete components also adds complexity in design. Furthermore, using an amplifier or comparator stage adds noise in the subsequent clock tree because amplifier or comparators are usually not optimized for phase noise performance like clock buffers. Figure 3-1 shows a generalized version of current approach without clock buffers. A better approach is to use integrated chip like clock buffer which has all the required circuity to amplify slow slew rates signals and optimized for all clocking parameters. Clock buffer converts the slow slew rate inputs to logic levels with very low additive phase noise, thus boosting the signal slew rate to also minimize phase noise degradation though the device in clock tree. Also, clock buffers reduces external BOM (bill of materials) depending on different features like internal biasing and AC coupling mode, and so on.

Generic Slew Rate Improvement Approach Figure 3-1 Generic Slew Rate Improvement Approach

TI has a wide portfolio of clock buffers that support sine wave input for single ended, differential and configurable buffers. TI clock buffers covers all the logic levels from LVCMOS (LMK1C110x), LVDS (LMK1D1xxx), LVPECL (CDCLVP12xx), and Universal buffers that support all industry standard output and inputs formats (LMK0030x, LMK01000, CDCLVC1310). This application note specifically uses LMK1C110x family of buffers for performance measurements due to inherent low additive phase noise.