Based on FSWP noise analyzer findings we performed the same experiment on TI PLL based synthesizer LMX2820. A 10MHz sine wave input at different power levels was injected directly and through the low noise buffer (LMK1C110x).

There were two cases in the experiment,

• Case 1: Sine wave input from SMA100B to LMX2820 at different power levels.
• Case 2: Sine wave input from SMA100B at same power levels as Case 1 amplified with LMK1C110x clock buffer into LMX2820.

Different power levels at the input were used to see the impact on the performance of PLL vs buffer input stage.

As shown in the Figure 5-3, there is significant improvement in phase noise of the PLL which results in improved jitter performance across different bands. PLL performance gap increases as we lower the power at 10MHz input reference shown between Trace 1 (Yellow) and Trace 4 (Orange) in Figure 5-3. This is due to further degradation in slew rate at the input.

At higher input frequencies shown in Figure 5-4, the performance gaps between the sine to square wave case gets smaller but if the input amplitude is small then buffer helps imporve phase noise.

Adding a buffer stage at lower power helps improve the performance margins in the system. Even at 14dBm and 10dBm (Trace 6: Red ) input power level, better slew rates from the clock buffer outperforms the PLL input stage. This shows that clock buffer can still be used even at higher power levels to further enhance the phase noise.

Following jitter measurement plots show the jitter impact at different bands when using the direct sinewave input to LMX2820 versus sinewave input through LMK1C110x clock buffer . Integrated jitter for the worst-case option improve approximately 5 times when using the clock buffer shown in Figure 5-11.