SNAA411 September   2024 CDCLVC1102 , CDCLVC1103 , CDCLVC1104 , CDCLVC1110 , CDCLVD1204 , LMK00301 , LMK00304 , LMK00306 , LMK00308 , LMK01801 , LMK04832 , LMK1C1102 , LMK1C1103 , LMK1C1104 , LMK1C1106 , LMK1C1108 , LMK1D1204 , LMK1D1208 , LMX2485 , LMX2491 , LMX2572 , LMX2592 , LMX2594 , LMX2595 , LMX2820

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Generic Clock Tree
  5. 2Sine Wave Slew Rate Requirement
  6. 3Current Approach vs Clock Buffer
  7. 4Clock Buffer Implementation
    1. 4.1 Clock Buffer Common Input Stages
    2. 4.2 Choosing Between Internal or External DC Bias
    3. 4.3 Single Ended or LVCMOS Signal
    4. 4.4 Differential Inputs
  8. 5Performance Improvements, Results With Clock Buffer
    1. 5.1 FSWP Phase Noise Analyzer Measurements Case
    2. 5.2 TI LMX2820 Noise Improvements With Sine to Square Wave Clock Buffer
      1. 5.2.1 LMX2820 Phase Noise and RMS Jitter Results Summary
  9. 6Sine to Square Wave Clock Buffer Comparison
    1. 6.1 LMK1C110x Additive Noise vs Others
  10. 7Summary
  11. 8References

4.3 Single Ended or LVCMOS Signal

Single ended or LVCMOS input stage detects 0 or 1 based on input signal level around threshold (Vt) point. VIH and VIL limits are recommended to avoid detection issues over temperature and voltage across multiple devices.

LVCMOS Thresholds Figure 4-4 LVCMOS Thresholds

To use sine wave with a LVCMOS buffers input stage, LVCMOS receiver threshold specification applies for the input signal. Since most of the time the sine wave signal generated from OCXO or other sources is centered around 0V DC offset. The input signal is re-biased to threshold Vt or VDD/2 value either externally or internally (if available).

Figure 4-5 shows a simplified diagram on biasing using voltage divider at the input. LMK1C110x use the same biasing configuration.

Re-biasing to LVCMOS Levels Figure 4-5 Re-biasing to LVCMOS Levels

R1 and R2 are same value resistor to get the VDD/2. Matching the transmission line impedance can be done with 100Ω resistor for both R1 and R2 which results in more power consumption due to higher current through the resistor. To reduce power consumption 1K or 10K resistor values can be used as well.

Table 4-1 Current Consumption for Voltage Divider
VDD 100Ω 1kΩ 10kΩ
3.3V 16.5mA 1.65mA 0.165mA
2.5V 12.5mA 0.125mA 0.125mA
1.8V 9mA 0.9mA 0.09mA