SNAA411 September   2024 CDCLVC1102 , CDCLVC1103 , CDCLVC1104 , CDCLVC1110 , CDCLVD1204 , LMK00301 , LMK00304 , LMK00306 , LMK00308 , LMK01801 , LMK04832 , LMK1C1102 , LMK1C1103 , LMK1C1104 , LMK1C1106 , LMK1C1108 , LMK1D1204 , LMK1D1208 , LMX2485 , LMX2491 , LMX2572 , LMX2592 , LMX2594 , LMX2595 , LMX2820

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Generic Clock Tree
  5. 2Sine Wave Slew Rate Requirement
  6. 3Current Approach vs Clock Buffer
  7. 4Clock Buffer Implementation
    1. 4.1 Clock Buffer Common Input Stages
    2. 4.2 Choosing Between Internal or External DC Bias
    3. 4.3 Single Ended or LVCMOS Signal
    4. 4.4 Differential Inputs
  8. 5Performance Improvements, Results With Clock Buffer
    1. 5.1 FSWP Phase Noise Analyzer Measurements Case
    2. 5.2 TI LMX2820 Noise Improvements With Sine to Square Wave Clock Buffer
      1. 5.2.1 LMX2820 Phase Noise and RMS Jitter Results Summary
  9. 6Sine to Square Wave Clock Buffer Comparison
    1. 6.1 LMK1C110x Additive Noise vs Others
  10. 7Summary
  11. 8References

4.2 Choosing Between Internal or External DC Bias

Generally, TI differential clock buffer families have two different DC biasing options, internal bias with small DC offset or internal DC bias with hysteresis. Both DC bias options are used to set the outputs to low state and avoid glitches on the outputs when there is loss of signal or clock. Figure 4-1 and Figure 4-2 shows both biasing techniques.

Internal DC Bias Offset ArchitectureFigure 4-1 Internal DC Bias Offset Architecture
Internal DC Bias with HysteresisFigure 4-2 Internal DC Bias with Hysteresis

Things to consider before opting for internal and external DC bias.

  • Check if the part has internal DC bias option, otherwise use external bias through a voltage divider. Internal bias at the inputs can be checked by probing the inputs with a high impedance on scope. Some TI devices offer VAC _REF pin for external biasing which can be used instead of voltage divider.
  • In case of internal DC bias with an offset at the input. External DC bias is recommended when using sine wave input to avoid duty cycle distortion on the output. Duty cycle distortion is result of sine wave imbalance at the switching threshold as shown in Figure 4-3.
  • When using large input signals at the differential input stage. Make sure that internal bias is good enough that the low or high level of the input signal doesn’t violate the input absolute maximum values in the data sheet. Otherwise re-bias the input signal with an external bias to avoid VIH and VIL absolute maximum values violations.
  • Refer to device data sheet for specific input termination needs due to any specific input requirements.
Duty Cycle Distortion with Imbalanced Sine Wave Figure 4-3 Duty Cycle Distortion with Imbalanced Sine Wave