SNAA411 September   2024 CDCLVC1102 , CDCLVC1103 , CDCLVC1104 , CDCLVC1110 , CDCLVD1204 , LMK00301 , LMK00304 , LMK00306 , LMK00308 , LMK01801 , LMK04832 , LMK1C1102 , LMK1C1103 , LMK1C1104 , LMK1C1106 , LMK1C1108 , LMK1D1204 , LMK1D1208 , LMX2485 , LMX2491 , LMX2572 , LMX2592 , LMX2594 , LMX2595 , LMX2820

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Generic Clock Tree
  5. 2Sine Wave Slew Rate Requirement
  6. 3Current Approach vs Clock Buffer
  7. 4Clock Buffer Implementation
    1. 4.1 Clock Buffer Common Input Stages
    2. 4.2 Choosing Between Internal or External DC Bias
    3. 4.3 Single Ended or LVCMOS Signal
    4. 4.4 Differential Inputs
  8. 5Performance Improvements, Results With Clock Buffer
    1. 5.1 FSWP Phase Noise Analyzer Measurements Case
    2. 5.2 TI LMX2820 Noise Improvements With Sine to Square Wave Clock Buffer
      1. 5.2.1 LMX2820 Phase Noise and RMS Jitter Results Summary
  9. 6Sine to Square Wave Clock Buffer Comparison
    1. 6.1 LMK1C110x Additive Noise vs Others
  10. 7Summary
  11. 8References

4.4 Differential Inputs

Input swing, amplitude, input common mode, and proper DC bias are important requirements to know when differential AC or DC coupled mode is used.

For sine wave input signals, INN pin or reference pin is always the biased at mid-point of active clock input signal. This avoids duty cycle distortion as shown below in the Figure 4-6.

Duty Cycle Distortion Figure 4-6 Duty Cycle Distortion

Following are some common DC re-bias techniques and considerations which are shared across TI devices.

  • AC Coupled Internal DC Bias Option: Most TI devices have internal DC bias of some sort that is specified in the data sheet. User can AC couple either single ended or differential inputs without the need for external components. For this type of use case, make sure to consider the input amplitude requirements, internal bias type specified for each device. AC coupled single ended internal options in shown in Figure 4-7.
  • AC Coupled External DC Bias Option: If there is no internal bias is available on the clock input of device or the duty cycle is a concern due to any DC offset between internal bias of INP and INN pins while dealing with smaller amplitude or sine wave input. External voltage divider is recommended to re-bias the signals to desired DC levels within the input common mode requirement of the device. External bias is helpful for start-up times because capacitors charging time can be controlled compared to internal weak bias option. An example of external bias for both single ended and differential case is shown in Figure 4-8.
  • DC Coupled single Ended Input using Differential Input: When using DC coupled LVCMOS or any other format single-ended waveform. INN or the unused input is set to the mid point of input signal as shown in Figure 4-9.
  • External DC Bias with VAC_Pin: Some TI devices offer a VAC_REF pin to re-bias inputs shown in Figure 4-10. This reduces start-up times while using fewer components than external DC bias option with voltage divider circuit.

Using differential inputs as single ended input case (sinewave or LVCMOS), if there is a need to reduce the input swing to meet data sheet input requirements, a 50Ω resistor to ground shown in Figure 4-7, Figure 4-8 andFigure 4-10 usually applied. Furthermore, INN pin also AC coupled to ground or left floating for single ended use case of differential inputs.

AC Coupled Internal DC Bias OptionFigure 4-7 AC Coupled Internal DC Bias Option
DC Coupled Single Ended Input with Differential Input StageFigure 4-9 DC Coupled Single Ended Input with Differential Input Stage
AC Coupled External DC Bias OptionFigure 4-8 AC Coupled External DC Bias Option
External DC Bias with VAC_REF Pin OptionFigure 4-10 External DC Bias with VAC_REF Pin Option