SNAU283 October 2022
Table 6-1 contains descriptions of the inputs and outputs for the evaluation board. Additionally, some applicable TICS Pro programming controls are noted for convenience.
| CONNECTOR NAME | SIGNAL TYPE, INPUT/OUTPUT | DESCRIPTION | ||
|---|---|---|---|---|
Clock Outputs Populated: CLKout0_P(J1), CLKout0_N(J2), CLKout1_P(J3), CLKout1_N(J4), CLKout2_P(J6), CLKout2_N(J5), CLKout3_P(J8), CLKout3_N(J7), CLKout4_P(J9), CLKout4_N(J10), CLKout5_P(J12), CLKout5_N(J11), CLKout6_P(J13), CLKout6_N(J14), CLKout7_P(J16), CLKout7_N(J15), CLKout8_P(J17), CLKout8_N(J18), CLKout9_P(J20), CLKout9_N(J19) | Analog, Output | Clock outputs with programmable output buffers. | ||
| The output terminations by default on the evaluation board are shown here: | ||||
| Clock Output Pair | Default Board Termination | |||
| CLKout0 | LVPECL / LCPECL, 240 Ω | |||
| CLKout1 | LVPECL / LCPECL, 240 Ω | |||
| CLKout2 | LVPECL / LCPECL, 120 Ω | |||
| CLKout3 | LVPECL / LCPECL, 120 Ω | |||
| CLKout4 | CML, 68 nH - 20 Ω | |||
| CLKout5 | CML, 50 Ω to Vcc | |||
| CLKout6 | CML, 68 nH - 20 Ω | |||
| CLKout7 | CML, 50 Ω to Vcc | |||
| CLKout8 | LVDS / HSDS | |||
| CLKout9 | LVDS / HSDS | |||
| Each CLKout pair has a programmable LVDS, LVPECL, LCPECL, HSDS, CML, or LVCMOS buffer. The output buffer type can be selected in the TICS Pro under the Clock Outputs page (Section 11.9) through the CLKoutX_FMT control. All clock outputs are AC-coupled to allow safe testing with RF test equipment. If an output pair is programmed to LVCMOS, each output can be independently configured (normal, inverted, or off/tri-state). Best performance/EMI reduction is achieved by using a complementary output mode like Norm/Inv. TI does NOT recommend using Norm/Norm or Inv/Inv mode. | ||||
Not Populated: CLKout10_P(J21), CLKout10_N(J22), CLKout11_P(J24), CLKout11_N(J23), CLKout12_P(J25), CLKout12_N(J26), CLKout13_P(J28), CLKout13_N(J27) | ||||
OSCout OSCout_P(J29) OSCout_N(J30) | Analog, Output | Buffered outputs of OSCin port. | ||
| The output terminations on the evaluation board are shown here.: | ||||
| OSC Output Pair | Default Board Termination | |||
| OSCout | LVPECL, 240 Ω | |||
| OSCout has a programmable LVDS, LVPECL, or LVCMOS output buffer. The OSCout buffer type can be selected in the TICS Pro under the Clock Outputs page (Section 11.9) through the OSCout_FMT control. OSCout is AC-coupled to allow safe testing with RF test equipment. If OSCout is programmed as LVCMOS, each output can be independently configured (normal, inverted, inverted, and off/tri-state). Best performance/EMI reduction is achieved by using a complementary output mode like Norm/Inv. TI does NOT recommend using Norm/Norm or Inv/Inv mode. | ||||
Power VccEXT(J39/J40/TP13) Vcc(TP12) | Power, Input | Main power supply input for the evaluation board. The LMK04368EPEVM default is setup to use the TPS7A4701-EP voltage regulator. This is a space grade (SEP) voltage regulator. 0-Ω resistors R93, R98 and R104 can be re-configured to route power through the on-board EP grade LDO, the TPS7A4701-EP. The LMK04368-EP contains internal voltage regulators for the VCO and other internal blocks. The clock outputs do not have an internal regulator, so a clean power supply with sufficient output current capability is required for optimal performance. If using an external voltage please ensure the voltage is filtered to get the best performance on the outputs. Apply power to either Vcc SMA(J39) or terminal block(J40), but not both. | ||
Clock Inputs CLKin0_P(J32), CLKin0_N(J31), CLKin1_P(J34), CLKin1_N(J33) OSCout_P(J29), OSCout_N(J30) Fin0_P(J37), Fin0_N(J38) | Analog, Input | Reference Clock Inputs for PLL1 or PLL1 (CLKin0, CLKin1, CLKin2) CLKin1_N is configured by default for a single-ended reference clock input from a 50-Ω source. The non-driven input pin CLKin1_P can be configured as R15 - DNI and R216 replace with 0-Ω resistor. CLKin0 is configured by default for a differential reference clock input from a 50-Ω source. CLKin1 is the default reference clock input selected in the TICS Pro. If OSCout is to be used as a CLKin2, then the PCB must be updated to operate as an input instead of an output. | ||
Clock Distribution with Fin0 or CLKin1/Fin1 Fin0 and CLKin1 (Fin1) are shared for use as an RF Input for Clock Distribution mode or for an external VCO mode. | ||||
External Feedback Input (FBCLKin) for 0-Delay CLKin1 is shared for use as an external feedback clock input (FBCLKin) to PLL1 N or PLL2 N for 0-delay mode. Refer to the LMK04368-EP data sheet for more details on using 0-delay mode with the evaluation board and the evaluation board software. | ||||
OSCin, PLL2 reference/PLL1 feedback OSCin_P(J36), OSCin_N(J35) | Analog, Input | Feedback VCXO clock input to PLL1 and Reference clock input to PLL2. The single-ended output of the onboard VCXO (Y1/Y2) drives the OSCin_N input of the device and the OSCin_P input of the device is connected to GND with 0.1 µF. VCXO Y1 and Y2 may also be used with differential VCXOs. An external VCXO may be optionally attached through these SMA connectors with minor modification to the components going to the OSCin pins of device. A single-ended or differential signal may be used to drive the OSCin pins and must be AC coupled. If operated in single-ended mode, the unused input must be connected to GND with 0.1 µF. Refer to the LMK04368-EP data sheet Electrical Characteristics table for PLL2 Reference Input (OSCin) specifications. | ||
VCO Tuning Voltages VTUNE1 (TP1/J41) VTUNE2 (TP2/J42) | Analog, Input/Output | Tuning voltage output from the loop filter for PLL1 and PLL2 of the LMK04368-EP. If an external VCXO is used, this tuning voltage can be connected to the voltage control pin of the external VCXO. The default board does not come with J41 and J42 populated. | ||
USB Connector USB connector (J45) SPI / GPIO Test points SDIO (TP11), SCK (TP8), CS* (TP4), CLKin_SEL0(TP9), CL Kin_SEL1(TP5). RESET(TP16), | CMOS, Input/Output | USB connector to program onboard USB2ANY device and configure the LMK04368-EP device through SPI interface. SPI signals include SDIO (TP11), SCK (TP8) and CS* (TP4) test points. The programmable logic I/O signals accessible through this header include: RESET (TP16), SYNC (TP10/J46), CLKin_SEL0 (TP9), and CLKin_SEL1 (TP5). | ||
Input Clock Switching – Pin Select Mode By default CLKin_SEL0 and CLKin_SEL1 are input pins. To enable input clock switching, CLKin_SEL_AUTO_EN = 0, CLKin_SEL_PIN_EN = 1, CLKin_SEL_PIN_POL = 0, and Status_CLKinX_TYPE must be 0 to 3 (pin enabled as an input). When CLKin_SEL_AUTO_EN = 0 and CLKin_SEL_PIN_EN = 1, the Status_CLKinX pins select which clock input is active as follows: | ||||
| CLKin_SEL1 | CLKin_SEL10 | Active Clock | ||
0 | 0 | CLKin0 | ||
0 | 1 | CLKin1 | ||
1 | 0 | CLKin2 | ||
1 | 1 | Holdover | ||
SYNC SYNC (TP10/J46) | CMOS, Input/Output | Programmable status I/O pin. By default, set as an input pin for synchronize the clock outputs with a fixed and known phase relationship between each clock output selected for SYNC. A SYNC event also causes the digital delay values to take effect. SYNC/SYSREF_REQ pin forces the SYSREF_MUX into SYSREF Continuous mode (0x03) when SYSREF_REQ_EN = 1. SYNC/SYSREF_REQ pin can hold outputs in a low state, depending on system configuration. SYNC_POL adjusts for active low or active high control. A SYNC event can also be programmed by toggling the SYNC_POL_INV bit in the SYNC/SYSREF page (Section 11.8) in the TICS Pro. | ||
Status LEDs Status_LD1(TP6), Status_LD2(TP7) | CMOS, Input/Output | Programmable status output pin. By default, Status_LD1 and Status_LD2 are set to output the digital lock detect status signal for PLL1 and the digital lock detect status signal for PLL2, respectively. By the default TICS Pro configuration, LEDs will illuminate green when lock is detected (output is high) and turn off when lock is lost (output is low). | ||