SNIU028D February 2016 – September 2020 UCD3138 , UCD3138064 , UCD3138064A , UCD3138128 , UCD3138A , UCD3138A64
Address 00050014 – DPWM 3 Event 2 Register
Address 00070014 – DPWM 2 Event 2 Register
Address 000A0014 – DPWM 1 Event 2 Register
Address 000D0014 – DPWM 0 Event 2 Register
17 | 0 |
EVENT2 |
R/W-0 0000 0011 0000 0000 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
17-0 | EVENT2 | R/W | 0 0000 0011 0000 0000 | Configures the location of Event 2. Value equals number of PCLK clock periods in Bits 17:4 and number of high resolution clock phases of PCL in Bits 3:0 (dependent on Bits 3:2 of DPWM Control Register 2). |