SNIU028D February 2016 – September 2020 UCD3138 , UCD3138064 , UCD3138064A , UCD3138128 , UCD3138A , UCD3138A64
There are three bit fields related to the Period interrupt.
PRD is the flag which indicates that there is a period interrupt occurring. It is only a strobed signal, so it is very unlikely that it will ever be read as set. If the interrupt bit is set, and no other bits are set, this means it is the period bit which has set it.
PRD_INT_EN enables the period interrupt.
PRD_INT_SCALE programs a divider for the period interrupt. The selections range from an interrupt every period to an interrupt every 256 periods. See the DPWM Reference section for the table.
Note that if the DPWM is disabled, under most circumstances, it will generate a period interrupt continuously, if the interrupt is enabled.