SNIU028D February 2016 – September 2020 UCD3138 , UCD3138064 , UCD3138064A , UCD3138128 , UCD3138A , UCD3138A64
Normally there is no need to read the status, but if there is, some precautions should be taken. The Watchdog Status Register is a clear on read register. The Watchdog is asynchronous to the CPU. On rare instances, it is possible to read from the register at exactly the right time and read a 0 even though the bit has been set and then cleared by the read.
To avoid this issue, set the interrupt enable bits in the WDCTRL register, even if the interrupts are not going to be used. Then poll the interrupt bits in the CIM to determine when the WD bits are set. Then it is safe to read from the WD status register to clear the bits, which will also clear the CIM bits.
Additionally, please note the following: