SNIU028D February 2016 – September 2020 UCD3138 , UCD3138064 , UCD3138064A , UCD3138128 , UCD3138A , UCD3138A64
Address 0x0008_0000 – Front End Control 2 Ramp Control Register
Address 0x000B_0000 – Front End Control 1 Ramp Control Register
Address 0x000E_0000 – Front End Control 0 Ramp Control Register
29 | 16 |
SYNC_FET_RAMP_START |
R/W-00 0000 0000 0000 |
15 | 13 | 12 | 11 | 10 | 9 | 8 |
Reserved | RAMP_SAT _EN | RAMP_COMP _INT_EN | RAMP_DLY _INT_EN | PREBIAS_INT _EN | PCM_START _SEL |
R-00 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SYNC_FET _EN | MASTER_SEL | SLAVE_COMP _EN | SLAVE_DELAY _EN | CONTROL_EN | FIRMWARE _START | RAMP_EN |
R/W-0 | R/W-00 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
29-16 | SYNC_FET _RAMP_START | R/W | 00 0000 0000 0000 | Provides the starting value for the SyncFET Ramp with a resolution of High Frequency Oscillator Period/bit |
15-13 | Reserved | R | 00 | |
12 | RAMP_SAT_EN | R/W | 0 | Enables addition or subtraction of DAC Saturation Step when EADC is in saturation. 0 = DAC Saturation Step logic is disabled, DAC incremented/decremented by value calculated by Ramp logic when EADC is in saturation (Default) 1 = DAC Saturation Step logic is enabled, DAC incremented/decremented by value stored in DAC Saturation Step register when EADC is in saturation |
11 | RAMP_COMP _INT_EN | R/W | 0 | Enables Ramp I/F Interrupt when soft-start/power-down ramp procedure is complete 0 = Soft-start/Power-Down Ramp Complete Interrupt is disabled (Default) 1 = Soft-start/Power-Down Ramp Complete Interrupt is enabled |
10 | RAMP_DLY _INT_EN | R/W | 0 | Enables Ramp I/F Interrupt when ramp delay procedure is complete 0 = Soft-start/Power-Down Ramp Delay Complete Interrupt is disabled (Default) 1 = Soft-start/Power-Down Ramp Delay Complete Interrupt is enabled |
9 | PREBIAS_INT_EN | R/W | 0 | Enables Ramp I/F Interrupt when Pre-Bias procedure is completed 0 = Pre-bias Complete Interrupt is disabled (Default) 1 = Pre-bias Complete Interrupt is enabled |
8 | PCM_START_SEL | R/W | 0 | Peak Current Mode Ramp Start Value Select 0 = Ramp starts from value programmed in DAC_VALUE bits in EADC_DAC_VALUE Register (Default) 1 = Ramp starts from filter output selected by PCM_FILTER_SEL bits in Loop Mux register PCMCTRL |
7 | SYNC_FET_EN | R/W | 0 | Enables SyncFET Ramp Operation 0 = SyncFET Ramp Operation disabled (Default) 1 = SyncFET Ramp Operation enabled |
6-5 | MASTER_SEL | R/W | 00 | Selects Master Ramp I/F in slave mode 0 = Front End Control 0 acts as master (Default) 1 = Front End Control 1 acts as master 2 = Front End Control 2 acts as master |
4 | SLAVE_COMP _EN | R/W | 0 | Enables syncing of ramp start to Master Ramp I/F Complete pulse 0 = Ramp initiated by Master Ramp Complete pulse disabled (Default) 1 = Ramp initiated by Master Ramp Complete pulse enabled |
3 | SLAVE_DELAY _EN | R/W | 0 | Enables syncing of ramp start to Master Ramp I/F Delay Complete pulse 0 = Ramp initiated by Master Ramp Delay Complete pulse disabled (Default) 1 = Ramp initiated by Master Ramp Delay Complete pulse enabled |
2 | CONTROL_EN | R/W | 0 | Enables PMBus Control line to initiate ramp 0 = PMBus Control does not initiate ramp (Default) 1 = PMBus Control initiates ramp |
1 | FIRMWARE _START | R/W | 0 | Ramp start bit, self-clearing by ramp logic 0 = No ramp sequence initiated by firmware (Default) 1 = Ramp sequence initiated by firmware |
0 | RAMP_EN | R/W | 0 | Enable Ramp Logic (Pre-biasing should be disabled before asserting ramp, bit 16 of Pre-Bias Control Register) 0 = No soft start or power-down ramp controlled by hardware (Default) 1 = Enables hardware control of soft start or power-down ramp |