SNIU028D February 2016 – September 2020 UCD3138 , UCD3138064 , UCD3138064A , UCD3138128 , UCD3138A , UCD3138A64
Address FFF7FD38 – 16-bit PWM0 Counter Control Register
Address FFF7FD5C – 16-bit PWM1 Counter Control Register
Address FFF7FD70 – 16-bit PWM2 Counter Control Register
Address FFF7FD84 – 16-bit PWM3 Counter Control Register
15 | 8 |
PRESCALE |
R/W-0000 0000 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | SYNC_SEL | SYNC_EN | SW_RESET | CMP_RESET_ENA | OV_INT_ENA | OV_INT_FLAG |
R-0 | R/W-00 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | PRESCALE | R/W | 0000 0000 | Defines the prescaler value to select the PWM counter resolution. Counter Resolution = (Prescaler + 1) *1/ICLK |
7 | Reserved | R | 0 | |
6-5 | SYNC_SEL | R/W | 00 | Configures master PWM counter 0 = PWM0 Counter (Default) 1 = PWM1 Counter 2 = PWM2 Counter 3 = PWM3 Counter |
4 | SYNC_EN | R/W | 0 | PWM counter starts when master PWM counter is enabled 0 = PWM counter independent of other PWM counters (Default) 1 = PWM counter controlled by Master PWM counter |
3 | SW_RESET | R/W | 0 | PWM counter reset by software. This bit is cleared after reset and has to be set to run the PWM counter. 0 = PWM counter reset and counter stop (Default) 1 = PWM counter is running |
2 | CMP_RESET_ENA | R/W | 0 | Enables PWM counter reset by compare action of T16CMPxDR. 0 = Disable PWM counter reset by compare action (Default) 1 = Enable PWM counter reset by compare action |
1 | OV_INT_ENA | R/W | 0 | PWM Counter Overflow Interrupt Enable 0 = Disable PWM counter overflow interrupt (Default) 1 = Enable PWM counter overflow interrupt |
0 | OV_INT_FLAG | R/W | 0 | Flag which indicates a PWM counter overflow. This bit is cleared by writing ‘1’ to it. If a clear and an overflow event occur at the same time, the flag will remain high (set has priority versus clear). 0 = No PWM counter overflow since last clear 1 = PWM counter overflow since last clear |