SNIU028D February 2016 – September 2020 UCD3138 , UCD3138064 , UCD3138064A , UCD3138128 , UCD3138A , UCD3138A64
Address FFF7FD04
15 | 8 | 7 | 3 | 2 | 1 | 0 |
PRESCALE | Reserved | EXT_ CLK_ SEL | OV_ INT_ ENA | OV_ FLAG |
R/W-0000 0000 | R-00000 | R/W-0 | R/W-0 | R-0 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | PRESCALE | R/W | 0000 0000 | Defines the prescaler value used to select the 24-bit counter resolution. The minimum divider ratio is 4, prescaler value less than 3 defaults to 3. Counter Resolution = (Prescaler Value+1)*1/ICLK |
7-3 | Reserved | R/W | 00000 | |
2 | EXT_CLK_SEL | R/W | 0 | External Clock Select 0 = Selects ICLK as clock for 24-bit counter (Default) 1 = Selects External Clock on FAULT-0 as clock for 24-bit counter |
1 | OV_INT_ENA | R/W | 0 | Counter Overflow Interrupt Enable 0 = Disables 24-bit Counter Overflow Interrupt (Default) 1 = Enables 24-bit Counter Overflow Interrupt |
0 | OV_FLAG | R | 0 | Indicates a counter overflow. Overflow event is cleared by writing a ‘1’ to this bit. If a clear and an overflow event occur at the same time, the flag will remain high (set has priority versus clear). 0 = No counter overflow since last clear 1 = Counter overflow since last clear |