SNIU028D February 2016 – September 2020 UCD3138 , UCD3138064 , UCD3138064A , UCD3138128 , UCD3138A , UCD3138A64
Address 0005007C – DPWM 3 Auto Config Mid Register
Address 0007007C – DPWM 2 Auto Config Mid Register
Address 000A007C – DPWM 1 Auto Config Mid Register
Address 000D007C – DPWM 0 Auto Config Mid Register
31 | 28 | 27 | 24 |
PWM_B_INTRA_MUX | PWM_A_INTRA_MUX |
R/W-000 | R/W-000 |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CBC_PWM_C _EN | MULTI_MODE _CLA_B_OFF | Reserved | CBC_PWM_AB _EN | CBC_ADV _CNT_EN | Reserved | MASTER _SYNC_CNTL _SEL |
R/W-0 | R/W-0 | R-0 | R/W-0 | R/W-0 | R-0 | R/W-0 |
15 | 14 | 13 | 12 | 11 | 8 |
Reserved | CBC_SYNC _CUR_LIMIT _EN | RESON_MODE _FIXED_DUTY_EN | Reserved |
R-0 | R/W-0 | R/W-0 | R-0000 0 |
7 | 6 | 4 | 3 | 2 | 1 | 0 |
Reserved | PWM_MODE | Reserved | CLA_EN | Reserved |
R-0000 0 | R/W-000 | R-00 | R/W-1 | R-0 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | PWM_B_INTRA _MUX | R/W | 000 | Interchanges DPWM signals post edge generation 0 = Pass-through (Default) 1 = Edge-gen output, this module 2 = PWM-C, this module 3 = Crossover, this module 4 = Pass-through (DPWM n+1)A 5 = Pass-through (DPWM n+1)B 6 = Pass-through (DPWM n+1)C 7 = Pass-through (DPWM n+2)C 8 = Pass-through (DPWM n+3)C |
27-24 | PWM_A_INTRA _MUX | R/W | 000 | Combines DPWM signals are prior to HR module 0 = Pass-through (Default) 1 = Edge-gen output, this module 2 = PWM-C, this module 3 = Crossover, this module 4 = Pass-through (DPWM n+1)A 5 = Pass-through (DPWM n+1)B 6 = Pass-through (DPWM n+1)C 7 = Pass-through (DPWM n+2)C 8 = Pass-through (DPWM n+3)C |
23 | CBC_PWM_C_EN | R/W | 000 | Sets if Fault CBC changes output waveform for PWM-C 0 = PWM-C unaffected by Fault CBC (Default) 1 = PWM-C affected by Fault CBC |
22 | MULTI_MODE _CLA_B_OFF | R/W | 0 | Configures control of PWM B output in Multi-Output Mode when CLA_ENABLE is asserted 0 = PWM B pulse width controlled by Filter Calculation (Default) 1 = PWM B pulse width controlled by Event3 and Event4 registers |
21 | Reserved | R | 0 | |
20 | CBC_PWM_AB _EN | R/W | 0 | Sets if Fault CBC changes output waveform for PWM-A and PWM-B 0 = PWM-A and PWM-B unaffected by Fault CBC (Default) 1 = PWM-A and PWM-B affected by Fault CBC |
19 | CBC_ADV_CNT _EN | R/W | 0 | Selects cycle-by-cycle of operation Normal Mode 0 = CBC disabled (Default) 1 = CBC enabled Multi and Resonant Modes 0 = PWM-A and PWM-B operate independently (Default) 1 = PWM-A and PWM-B pulse matching enabled |
18-17 | Reserved | R | 00 | |
16 | MASTER_SYNC _CNTL_SEL | R/W | 0 | Configures master sync location 0 = Master Sync controlled by Phase Trigger Register (Default) 1 = Master Sync controlled by CLA value |
15-14 | Reserved | R | 00 | |
13 | CBC_SYNC_CUR _LIMIT_EN | R/W | 0 | Sets how current limit affects slave sync 0 = Slave sync is unaffected during current limit (Default) 1 = Slave sync is advanced during current limit. |
12 | RESON_MODE _FIXED_DUTY _EN | R/W | 0 | Configures how duty cycle is controlled in Resonance Mode 0 = Resonant mode duty cycle set by Filter duty (Default) 1 = Resonant mode duty cycle set by Auto Switch High Register |
11-7 | Reserved | R | 0000 0 | |
6-4 | PWM_MODE | R/W | 000 | DPWM Mode 0 = Normal Mode (Default) 1 = Resonant Mode 2 = Multi-Output Mode 3 = Triangular Mode 4 = Leading Mode |
3-2 | Reserved | R | 00 | |
1 | CLA_EN | R/W | 1 | CLA Processing Enable 0 = Generate PWM waveforms from PWM Register values 1 = Enable CLA input (Default) |
0 | Reserved | R | 0 |