SNIU028D February 2016 – September 2020 UCD3138 , UCD3138064 , UCD3138064A , UCD3138128 , UCD3138A , UCD3138A64
Address FFFFFFE4
The System Exception Status Register contains flags for different reset/abort sources. On power-up, all bits are cleared to 0. When a reset condition is recognized, the appropriate bit in the Register is set and the value of the bit is maintained through the reset. When a new reset condition occurs, the current contents of this Register are not cleared. The contents of this Register are cleared on a power-on reset or by software.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PORRST | CLKRST | WDRST | ILLMODE | ILLADR | ILLACC | PILLACC | ILLMAP |
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
7 | 6 | 0 |
SWRST | Reserved |
R/W-0 | R-000 0000 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | PORRST | R/W | 0 | Power-On reset flag. Set when power-on reset is asserted. Reset is asserted as long as power-on-reset is active. Whenever a device is powered, this bit is set. User and privilege modes (read 0 = Power-up reset has not occurred since the last clear 1 = Power-up reset has occurred since the last clear User and privilege modes (write) 0 = Clears the corresponding bit to 0 1 = No effect |
14 | CLKRST | R/W | 0 | This bit represents the clock fail flag. This bit indicates a clock fault condition has occurred. After power-on-reset, the CLKRST is reset to 0. Value remains unchanged during other resets. User and privilege modes (read) 0 = Clock failure has not occurred since the last clear 1 = Clock failure has occurred since the last clear User and privilege modes (write) 0 = Clears the corresponding bit to 0 1 = No effect |
13 | WDRST | R/W | 0 | This bit represents the watchdog reset flag. This bit indicates that the last reset was caused by the watchdog. User and privilege modes (read 0 = Watchdog reset has not occurred since the last clear 1 = Watchdog reset has occurred since the last clear User and privilege modes (write) 0 = Clears the corresponding bit to 0 1 = No effect |
12 | ILLMODE | R/W | 0 | This bit represents the illegal mode flag. This bit is set when the mode bits in the program status Register are set to an illegal value. User and privilege modes (read) 0 = Illegal mode has not occurred since the last clear 1 = Illegal mode has occurred since the last clear User and privilege modes (write) 0 = Clears the corresponding bit to 0 1 = No effect |
11 | ILLADR | R/W | 0 | This bit represents the illegal address access flag. This bit is set when an access to an unimplemented location in the memory map is detected in non-user mode. User and privilege modes (read) 0 = Illegal address has not occurred since the last clear 1 = Illegal address has occurred since the last clear User and privilege modes (write) 0 = Clears the corresponding bit to 0 1 = No effect |
10 | ILLACC | R/W | 0 | This bit represents the illegal memory access flag. This bit is set when an access to a protected location without permission rights is detected in non-user mode. User and privilege modes (read) 0 = Illegal memory access has not occurred since the last clear 1 = Illegal memory access has occurred since the last clear User and privilege modes (write) 0 = Clears the corresponding bit to 0 1 = No effect |
9 | PILLACC | R/W | 0 | This bit represents the peripheral illegal access flag. This bit is set when a peripheral access violation is detected in user mode. User and privilege modes (read) 0 = Illegal peripheral access has not occurred since the last clear 1 = Illegal peripheral access has occurred since the last clear User and privilege modes (write) 0 = Clears the corresponding bit to 0 1 = No effect |
8 | ILLMAP | R/W | 0 | This bit represents the illegal address map flag. This bit is set when the base addresses of one or more memories overlap. Reset occurs when the overlapped registration is accessed. User and privilege modes (read) 0 = Illegal address mapping has not occurred since the last clear 1 = Illegal address mapping has occurred since the last clear User and privilege modes (write) 0 = Clears the corresponding bit to 0 1 = No effect |
7 | SWRST | R/W | 0 | This bit represents the software reset flag. This bit is set when the last reset is caused by software writing the RESET bits. User and privilege modes (read) 0 = Software reset has not occurred since the last clear 1 = Software reset has occurred since the last clear User and privilege modes (write) 0 = Clears the corresponding bit to 0 1 = No effect |
6-0 | Reserved | R | 000 0000 |