SNIU028D February 2016 – September 2020 UCD3138 , UCD3138064 , UCD3138064A , UCD3138128 , UCD3138A , UCD3138A64
Address FFFFFFEC
The Global Status Register specifies the module that triggered the illegal address, illegal access, abort or reset. When a new reset condition reset occurs, the current contents of this Register are not cleared. The contents of this Register are cleared on a power-on reset or by software.
7 | 6 | 5 | 4 | 3 | 0 |
SYSADDR | SYSACC | MPUADDR | MPUACC | Reserved |
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R-0000 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | SYSADDR | R/W | 0 | This bit represents the system illegal address flag. This bit is set when the system detects an illegal address. User and privilege modes (read) 0 = No system illegal address 1 = Abort or reset caused by a system illegal address User and privilege modes (write) 0 = Clears bit to 0 1 = No effect |
6 | SYSACC | R/W | 0 | This bit represents the system illegal access flag. This bit is set when the system detects an illegal access. User and privilege modes (read) 0 = No system illegal access 1 = Abort or reset caused by a system illegal access User and privilege modes (write) 0 = Clears bit to 0 1 = No effect |
5 | MPUADDR | R/W | 0 | This bit represents the MPU illegal address flag. This bit is set when the memory protection unit detects an illegal address. User and privilege modes (read) 0 = No MPU illegal address 1 = Abort or reset caused by a MPU illegal address User and privilege modes (write) 0 = Clears bit to 0 1 = No effect |
4 | MPUACC | R/W | 0 | This bit represents the MPU illegal access flag. This bit is set when the MPU detects an illegal access. User and privilege modes (read) 0 = No MPU illegal access 1 = Abort or reset caused by a MPU illegal access User and privilege modes (write) 0 = Clears bit to 0 1 = No effect |
3-0 | Reserved | R | 0000 |