SNIU028D February 2016 – September 2020 UCD3138 , UCD3138064 , UCD3138064A , UCD3138128 , UCD3138A , UCD3138A64
Address FFFFFF2C
A 32-bit FIQ/IRQ program control Register (FIRQPR) determines whether a given interrupt request will be FIQ or IRQ type.
31 | 0 |
FIRQPR |
R/W-0000 0000 0000 0000 0000 0000 0000 0000 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | FIRQPR | R/W | 0000 0000 0000 0000 0000 0000 0000 0000 | These bits determine whether an interrupt request from a peripheral is of type FIQ or IRQ. Each bit corresponds to one request channel. This Register is writeable in privilege mode only. 0 = Interrupt request is of IRQ type (Default) 1 = Interrupt request is of FIQ type |