SNIU028D February 2016 – September 2020 UCD3138 , UCD3138064 , UCD3138064A , UCD3138128 , UCD3138A , UCD3138A64
Address 00020074
18 | 17 | 16 | 15 | 10 |
BIST_COMP | BIST_EN | EADC_TRIM_TEST_EN | EADC_REF_TRIM |
R-0 | R/W-0 | R/W-0 | R/W-000000 |
9 | 8 | 7 | 2 | 1 | 0 |
EADC_REF_RESET | EADC_REF_EN | GAIN_TRIM | AFE_GAIN |
R/W-1 | R/W-0 | R/W-0000 00 | R/W-11 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
18 | BIST_COMP | R | 0 | High-Speed Loop BIST Complete Status 0 = High-Speed Loop BIST not complete 1 = High-Speed Loop BIST completed |
17 | BIST_EN | R/W | 0 | High-Speed Loop BIST Enable 0 = High-Speed Loop BIST disabled (Default) 1 = High-Speed Loop BIST enabled |
16 | EADC_TRIM _TEST_EN | R/W | 0 | EADC Trim Test Mode Enable 0 = EADC Trim Test Mode disabled (Default) 1 = EADC Trim Test Mode enabled, bits 15:0 provided to all 3 Analog Front End modules |
15-10 | EADC_REF_TRIM | R/W | 000000 | EADC Reference Trim Value. Bits will be programmed during test and should not be overwritten by firmware. |
9 | EADC_REF _RESET | R/W | 1 | EADC Reference Reset 0 = Reference not in reset 1 = Resets Reference (Default) |
8 | EADC_REF_EN | R/W | 0 | EADC Reference Enable 0 = Disables EADC Reference (Default) 1 = Enables EADC Reference |
7-2 | GAIN_TRIM | R/W | 0000 00 | Sets trim for EADC Gain. |
1-0 | AFE_GAIN | R/W | 11 | AFE Front End Gain Setting 0 = 1x Gain, 8mV/LSB 1 = 2x Gain, 4mV/LSB 2 = 4x Gain, 2mV/LSB 3 = 8x Gain, 1mV/LSB (Default) |