SNIU028D February 2016 – September 2020 UCD3138 , UCD3138064 , UCD3138064A , UCD3138128 , UCD3138A , UCD3138A64
Address 0005005C – DPWM 3 Minimum Duty Cycle Low Register
Address 0007005C – DPWM 2 Minimum Duty Cycle Low Register
Address 000A005C – DPWM 1 Minimum Duty Cycle Low Register
Address 000D005C – DPWM 0 Minimum Duty Cycle Low Register
17 | 4 | 3 | 0 |
MIN_DUTY_LOW | Reserved |
R/W-00 0000 0000 0000 | R-0000 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
17-4 | MIN_DUTY_LOW | R/W | 00 0000 0000 0000 | Configures lower threshold for minimum duty cycle logic. Low resolution register, last 4 bits are read-only. |
3-0 | Reserved | R | 0000 |