SNIU028D February 2016 – September 2020 UCD3138 , UCD3138064 , UCD3138064A , UCD3138128 , UCD3138A , UCD3138A64
Address FFF7FD3C – 16-bit PWM0 Compare Channel 0 Data Register
Address FFF7FD40 – 16-bit PWM0 Compare Channel 1 Data Register
Address FFF7FD60 – 16-bit PWM1 Compare Channel 0 Data Register
Address FFF7FD64 – 16-bit PWM1 Compare Channel 1 Data Register
Address FFF7FD74 – 16-bit PWM2 Compare Channel 0 Data Register
Address FFF7FD78 – 16-bit PWM2 Compare Channel 1 Data Register
Address FFF7FD88 – 16-bit PWM3 Compare Channel 0 Data Register
Address FFF7FD8C – 16-bit PWM3 Compare Channel 1 Data Register
15 | 0 |
CMP_DAT |
R/W-0000 0000 0000 0000 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | CMP_DAT | R/W | 0000 0000 0000 0000 | Contains the 16-bit compare value. When in PWM mode, the value in the T16PWMxCMPyDAT is loaded after a match with the PWMx Counter Data Register. When in OC mode, it has to be written by the CPU. The mode is controlled by the bit SHADOW in the PWMx/Dual Compare Control Register. If both Registers T16PWMxCMP0DAT and T16PWMxCMP1DAT contain the same value, the interrupt and pin behavior is controlled by output compare channel 0 (T16PWMxCMP0DAT has priority over T16PWMxCMP1DAT). |