Multipoint networks provide designers
with an economical and simple method to interface multiple devices using a single
interconnect or a bus. While simplicity and low cost make multipoint networks
appealing for many, designing these networks is never a straightforward task. The
following list provides design guidelines for implementing reliable M-LVDS
multipoint networks.
- Design or select interconnects
that are optimal for multipoint networks. In a multipoint network, each port
presents a load to the bus. The loads are typically capacitive consisting of
M-LVDS I/O capacitance and intrinsic capacitance of the stubs. A capacitive load
on a bus with uniform impedance lowers the impedance of the bus at the port
location and creates impedance mismatches. When multiple loads are connected on
a bus with relatively uniform spacing between the loads, the overall
characteristic impedance of the bus becomes lower. Lower characteristic
impedance of the bus requires lower value termination resistors. Lower value
termination resistors mean lower DC load for a signal driver and ultimately
lower signal amplitude. Even though the M-LVDS drivers feature control circuitry
that keeps output amplitude constant, the output amplitude is only constant for
a load of 40Ω or higher. This means that the differential characteristic
impedance of the loaded bus needs to be 80Ω or higher. To achieve this, select
or design a bus with higher than nominal (100Ω differential) characteristic
impedance so that its impedance does not go below 80Ω when fully loaded.
- Select M-LVDS drivers with the
slowest transition time that will satisfy the bandwidth requirements of the
system. Drivers that have transition times of one half of the unit interval (UI)
at the bit rate of interest provide the highest noise margin. For example, the
M-LVDS drivers have typical transition times of 2 ns. This makes them ideal for
operation at 250 Mbps/125 MHz (4 ns UI). At 250 Mbps, any reflections that may
occur in the bus have energy that is only at the frequencies that are multiples
of the Nyquist frequency (125 MHz). With this distribution of the signal energy,
reflections that have energy at the frequencies that are higher than the Nyquist
frequency are absent. The reflections that have energy at frequencies higher
than the Nyquist frequency are a serious threat to signal distribution in
multipoint networks.
- Minimize the length of stubs as
much as possible. M-LVDS devices are typically fine with stubs that are 1 inch
(2.5 cm) or shorter (Connector electrical length should be considered when
determining the total stub length). Anything longer than that may cause a system
to fail. Experimental data presented in the application note AN-1503 has shown
that shortening the stubs from 1 to 1/2 inches may increase noise margin by as
much as 50%. In addition, when noise margin is at premium, one should consider
maximizing the stub impedance. This can be accomplished by increasing the
dielectric thickness of the material, reducing the stub width, and uncoupling or
loosely coupling the individual traces of the stub.
- Place M-LVDS drivers next to
termination resistors provided other system constrains allow it. The worst
driver location is in the middle of a multipoint network; the receivers adjacent
to the driver always have the worst noise margin. By placing the drivers at one
end of the network close to one of the two termination resistors, network
topologies with longer signal paths are created. The longer signal paths have
more loss and as result increase transition times of the signal as it propagates
from the driver toward the furthest receiver. Slower transition times are more
“forgiving” when encountering impedance discontinuities.
- Any power supply noise reduces
available noise margin. Ensure that M-LVDS devices are properly decoupled. Each
VDD or GND pin of an M-LVDS device should be connected to a
printed circuit board (PCB) through a low inductance path. For best results, one
or more vias should be used to connect a VDD or GND pin to the nearby
plane. Ideally, via placement is immediately adjacent to the pin to avoid adding
intrinsic trace inductance. Bypass capacitors should be placed close to
VDD pins. Small physical size capacitors, such as 0402, X7R,
surface mount capacitors should be used to minimize package inductance of
capacitors. Each bypass capacitor should be connected to the power and ground
planes through vias tangent to the pads of the capacitor. An X7R surface mount
capacitor of size 0402 has about 0.5 nH of body inductance. At frequencies above
30 MHz or so, X7R capacitors behave as low impedance inductors. To extend the
operating frequency range to a few hundred MHz, an array of different capacitor
values such as 100 pF, 1 nF, 0.03 µF, and 0.1 µF are commonly used in parallel.
The most effective bypass capacitor can be built using sandwiched layers of
power and ground at a separation of 2–3 mils. With a 2 mil FR-4 dielectric,
there is approximately 500 pF per square inch of a PCB. For devices packaged in
LLP packages (e.g. DS91M040), the die attach pad (DAP) should be connected to a
ground plane through an array of vias. The via array reduces the effective
inductance to ground and enhances the thermal performance of the LLP
package.