SNLA404 December 2022 DP83TC811R-Q1 , DP83TC811S-Q1 , DP83TC812R-Q1 , DP83TC812S-Q1 , DP83TG720R-Q1 , DP83TG720S-Q1
At TB (relative to T0), the PHY is able to be accessible via SMI access. MDC and MDIO are used for this communication.
811 |
720 |
812 |
|
---|---|---|---|
TB (ms) |
60 |
60 |
60 |
Figure 2-4 shows the MDC and MDIO timing diagram. The pairs are separated as the write timing diagram is above the read diagram. Within the pairs, MDC is above MDIO. Please be aware that some PHYs can require 32 bits of preamble for the synchronization purposes.