SNLA426 june   2023 DS320PR1601 , DS320PR410

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 PCIe Gen3, Gen4, and Gen5 Loss Budget
  6. 3 Minimum Eye Width
  7. 4 Cross Talk Mitigation
  8. 5 Humidity and Temperature Insertion Loss
  9. 6 Critical Signals
  10. 7 General High-Speed Signal Routing
  11. 8 PCB Grain and Fiber Weave Selection
  12. 9 PCB Material Loss Budget
  13. 10High-Speed Signal Trace Impedance
  14. 11High-Speed Signal Trace Length Matching
  15. 12Differential Trace Routing Guidelines
  16. 13Differential-Inter-Pair Matching
  17. 14Intra-pair Length Matching
  18. 15Trace Bends
  19. 16Minimum Differential Trace-To-Trace Distance
  20. 17Serpentine Guidelines
  21. 18High-Speed Differential Signal Quick Rules
  22. 19High-Speed Differential Pair Reference Plane
  23. 20Via Staggering
  24. 21Via Stubs
  25. 22Via Pads
  26. 23Via Discontinuity Mitigation
  27. 24Back-Drill Stubs
  28. 25AC Coupling Capacitors Placement
  29. 26AC Coupling Capacitor Physical Placement
  30. 27Auxiliary Signal AC Match Termination
  31. 28Suggested PCB Stack-ups
  32. 29Summary
  33. 30References

23 Via Discontinuity Mitigation

A via presents a short section of change in geometry to a trace and can appear as a capacitive and or an inductive discontinuity. These discontinuities result in reflections and some degradation of a signal as it travels through the via. Reducing the overall via stub length to minimize the negative impacts of vias (and associated via stubs).

Because longer via stubs resonate at lower frequencies and increase insertion loss, keep via stubs as short as possible. In most cases, the stub portion of the via presents significantly more signal degradation than the signal portion of the via. Guidelines for vias are presented as follows:

  1. PCIe Gen5 20/80% rise/fall time is 12 ps. To preserve this type of rise and fall time, approximately 29 GHz bandwidth (0.35/0.12(ns) rule) is required. At this bandwidth and using Megtron 6 (εr approximately 3.4), the resulting quarter wavelength is approximately 54 mils. This result means the stub has to be less than this length if back drilling is not implemented.
    1. This is the same reason why for a typical FR4 (εr approximately 4.2) PCB, the maximum stub length is approximately 51 mils.
  2. For vias, follow the 10/20/40 drill/pad/anti-pad rule. See Figure 23-1
  3. It is best to optimize anti-pad size by simulation – this is highly dependent on the board stack-up.
  4. GND stitches around the anti-pad must be used – as many as possible to improve the current return path given the reference layer is changing. See Figure 23-1.
  5. Closely coupled vias need to be used to optimize target impedance.
  6. A short stub exhibits less or better reflection, but it can create more cross talk. Also, a long stub shows worse reflection but lower cross talk. During PCB simulation, cross talk versus reflection needs to be mitigated.
  7. Consider GND flooding with very short GND stitches. This process prevents supply coupling capacitor via on pad.
  8. If possible, use via-in-pad versus a traditional via to reduce the overall inductance of the pad. See Figure 22-1 for an example.
  9. If using vias is necessary on a high-speed differential signal trace, make sure that the via count on each member of the differential pair is equal and that the vias are as equally spaced as possible. TI recommends placing vias as close as possible to the PCIe device.
GUID-20230510-SS0I-TGCZ-5SS5-DM14CW6GPTDD-low.svgFigure 23-1 Pad Layout Example