SNLA433 august   2023 DS320PR1601 , DS320PR410 , DS320PR810 , SN75LVPE5412 , SN75LVPE5421

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Device Overview
    1. 2.1 Receiver Equalization
    2. 2.2 Redriver Linearity
    3. 2.3 PCIe Links with Linear Redrivers
    4. 2.4 Redriver EQ Tuning
      1. 2.4.1 Detailed Description of Parameters Calibration
  6. 3General Guidelines for Optimal CTLE and Gain Selection
  7. 4Summary
  8. 5References

Redriver EQ Tuning

In most cases, PCIe Gen5 redrivers require tuning the CTLE setting to provide satisfactory eye openings. The recommendation is to leave DC gain at the default setting of 0 dB. Refer to PCI Express Compliance Testing with the DS320PR810 for direct effects of DC gain and equalization settings.

Receiver link equalization compliance is done on system or Add-In-Cards to verify interoperability at 1E-12 under stressed conditions. First, different parameters calibration is done to provide the same environment for different systems or AIC applications. The following setups are used for the RX EQ compliance adherence. Images are courtesy of PCI-SIG.

GUID-20230803-SS0I-5WWC-6ZH2-PZ1WPB262HWD-low.pngFigure 2-7 PCI-SIG AIC RX Calibration Specifications
GUID-20230803-SS0I-NP6G-5RD4-NW7XF73XVGNK-low.pngFigure 2-8 PCI-SIG System RX Calibration Specifications
Note: Whether in a system or AIC scenario, VNA port 1 and 3, and the block are used by the PCIe aware BERT to put the link partner one lane into loopback mode through protocol. Using calibrated stressed eye, 1E-12 BER one error or less needs to be achieved.
GUID-20230803-SS0I-5RP7-WQHJ-WK18N96F8HPC-low.pngFigure 2-9 PCIe Gen5 SI, CBB, and CLB Boards
GUID-20230803-SS0I-BBRL-5LFC-GV5CRSH49MCS-low.pngFigure 2-10 RX Compliance Block Diagram