SNLA433A August 2023 – December 2024 DS320PR1601 , DS320PR410 , DS320PR810 , SN75LVPE5412 , SN75LVPE5421
Tuning the PCIe Gen5 linear redriver is one of the main tasks when designing a line card based on a linear redriver. The linear nature is important. PCIe negotiation requires link training to achieve suitable signaling conditions across pre-redriver and post-redriver (pre- or post-channel loss) profiles. To accomplish this goal, different levels of the pre-shoot and post-shoot (or de-emphasis) are exchanged between the Root Complex (RC) and the End Point (EP) to compensate for the overall channel loss profile. A linear redriver must act like a seamless entity and operate in its linear region to enhance high frequency content without compressing the signals. An incorrect tuning can compress or over-equalize these signals, resulting in degraded performance and/or difficulties with link training. Linear operation of the device allows Continuous Time Linear Equalization (CTLE) and Decision Feedback Equalization (DFE) on both sides of the redriver to train up normally.
This application note discusses key features of the redriver relevant to the PCIe negotiation and provides pre- and post- channel loss analysis to help fine-tune and facilitate redriver CTLE settings. This document includes validation and system level results, suggests recommendations for redriver placement, outlines possible PCIe link extensions, and provides redriver step-by-step tuning instructions using real system examples. With a complete understanding of redriver capabilities, limitations, and tuning steps, system designers are better equipped to extend the reach of PCIe 5.0 links using linear redrivers.