The strap values can be read from registers 0x467 (SOR_1) and 0x468 (SOR2), these registers are extended registers and can only be accessed using Extended Register Access. In the cases that the read strap value differs from the desired strap configurations, the voltage levels of the strap pins can be measured. Measurements can be made during power up and after power up when the RESET_N signal is asserted. Strap configurations can also be verified with the strap tool built in the DP83822 Schematic Checklist.

The DP83822 uses the receive path functional pins as bootstrap options to place the device into specific modes of operation. The values of these pins are sampled at power up or hardware reset, through either the RESET pin or bit[15] in the PHY Reset Control Register (PHYRCR, address 0x001F). The DP83822 bootstrap pins are 4-level, which are described in greater detail below. Because bootstrap pins may have alternate functions after reset is de-asserted, they should not be connected directly to VCC or GND. Pullup and pulldown resistors are required for proper operation.

Configuration of the device may be done via 4-level strapping or via serial management interface. A pullup resistor and a pulldown resistor of suggested values should be used to set the voltage ratio of the bootstrap pin input and the supply to select one of the possible modes.