SNLS545E March   2017  – July 2022 LMH1297

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Recommended SMBus Interface Timing Specifications
    7. 7.7 Serial Parallel Interface (SPI) Timing Specifications
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  4-Level Input Pins and Thresholds
      2. 8.3.2  Equalizer (EQ) and Cable Driver (CD) Mode Control
        1. 8.3.2.1 EQ/CD_SEL Control
        2. 8.3.2.2 OUT0_SEL and SDI_OUT_SEL Control
      3. 8.3.3  Input Carrier Detect
      4. 8.3.4  –6-dB Splitter Mode Launch Amplitude for SDI_IO+ (EQ Mode Only)
      5. 8.3.5  Continuous Time Linear Equalizer (CTLE)
        1. 8.3.5.1 Line-Side Adaptive Cable Equalizer (SDI_IO+ in EQ mode)
        2. 8.3.5.2 Host-Side Adaptive PCB Trace Equalizer (IN0± in CD Mode)
      6. 8.3.6  Clock and Data (CDR) Recovery
      7. 8.3.7  Internal Eye Opening Monitor (EOM)
      8. 8.3.8  Output Function Control
      9. 8.3.9  Output Driver Control
        1. 8.3.9.1 Line-Side Output Cable Driver (SDI_IO+ in CD mode, SDI_OUT+ in EQ or CD mode)
          1. 8.3.9.1.1 Output Amplitude (VOD)
          2. 8.3.9.1.2 Output Pre-Emphasis
          3. 8.3.9.1.3 Output Slew Rate
          4. 8.3.9.1.4 Output Polarity Inversion
        2. 8.3.9.2 Host-Side 100-Ω Output Driver (OUT0± in EQ or CD mode)
      10. 8.3.10 Status Indicators and Interrupts
        1. 8.3.10.1 LOCK_N (Lock Indicator)
        2. 8.3.10.2 CD_N (Carrier Detect)
        3. 8.3.10.3 INT_N (Interrupt)
      11. 8.3.11 Additional Programmability
        1. 8.3.11.1 Cable EQ Index (CEI)
        2. 8.3.11.2 Digital MUTEREF
    4. 8.4 Device Functional Modes
      1. 8.4.1 System Management Bus (SMBus) Mode
        1. 8.4.1.1 SMBus Read and Write Transaction
          1. 8.4.1.1.1 SMBus Write Operation Format
          2. 8.4.1.1.2 SMBus Read Operation Format
      2. 8.4.2 Serial Peripheral Interface (SPI) Mode
        1. 8.4.2.1 SPI Read and Write Transactions
        2. 8.4.2.2 SPI Write Transaction Format
        3. 8.4.2.3 SPI Read Transaction Format
        4. 8.4.2.4 SPI Daisy Chain
    5. 8.5 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 SMPTE Requirements and Specifications
      2. 9.1.2 Low-Power Optimization in CD Mode
      3. 9.1.3 Optimized Loop Bandwidth Settings for Arria 10 FPGA Applications
    2. 9.2 Typical Applications
      1. 9.2.1 Bidirectional I/O
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Cable Equalizer With Loop-Through
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Board Stack-Up and Ground References
      2. 11.1.2 High-Speed PCB Trace Routing and Coupling
        1. 11.1.2.1 SDI_IO± and SDI_OUT±:
        2. 11.1.2.2 IN0± and OUT0±:
      3. 11.1.3 Anti-Pads
      4. 11.1.4 BNC Connector Layout and Routing
      5. 11.1.5 Power Supply and Ground Connections
      6. 11.1.6 Footprint Recommendations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

4 Revision History

Changes from Revision D (May 2020) to Revision E (July 2022)

  • Updated the numbering format for tables, figures, and cross-references throughout the documentGo
  • Added inclusive terminology throughout the data sheetGo
  • Changed CDON_IN0 and CDOFF_IN0 Test Condition to "11.88 Gbps PRBS10 pattern"Go
  • Removed 12G/6G from VDC_WANDER Test ConditionGo
  • Added table note to Serial Parallel Interface (SPI) Timing SpecificationsGo
  • Updated Line-Side Adaptive Cable Equalizer (SDI_IO+ in EQ mode)Go
  • Updated Line-Side Output Cable Driver (SDI_IO+ in CD mode, SDI_OUT+ in EQ or CD mode)Go

Changes from Revision C (July 2019) to Revision D (May 2020)

  • Changed HBM ESD rating and added pin 27 description Go

Changes from Revision B (September 2017) to Revision C (July 2019)

  • First public release of document.Go

Changes from Revision A (July 2017) to Revision B (September 2017)

  • Changed NTpsmax test condition max from 6 GHz to 50 MHz and < 20 mVp-p NOM to < 10 mVp-p Go
  • Changed tR_F_SDI minimum SD rise/fall time from 390 ps to 400 ps due to incorrect default settingsGo
  • Changed typical tR/tF of OUT0 from 35 ps to 45 ps Go
  • Added PRBS10 pattern to clarify AJCD_MODE and TMJCD_MODE Test ConditionGo
  • Added SMBUS SCL min frequency per SMBus 2.0 specifications Go
  • Added Figure 7-1 to clarify definition of SMBus Timing Parameters in Section 7.6 Go
  • Added typical characteric curves for OUT0 VOD and de-emphasis vs. LMH1297 register settingsGo
  • Added default internal pullup and pulldown settings for 2-level strap pins in Figure 9-1 Go
  • Added clarification in Table 9-1 regarding reclocker behavior when used with non-SDI data rates Go
  • Changed Step 6 description in Section 9.2.1.2 to include both pin and register settings to switch between EQ mode and CD mode.Go

Changes from Revision * (March 2017) to Revision A (July 2017)

  • Changed typical power consumption in CD mode from 315 mW to 305 mW based on updated characterization data Go
  • Changed typical and maximum current dissipation based on updated complete characterization dataGo
  • Changed maximum current dissipation when acquiring lock based on updated complete characterization dataGo
  • Changed TMJCD_MODE maximum spec from 8 UI to 0.45 UI typical because parameter is system dependent Go
  • Added tablenote to optimize PLL bandwidth for 11.88 Gbps Go
  • Changed Digital MUTEREF description to apply to SDI_IO+, not IN0+ Go
  • Added the Section 9.1.3 sectionGo
  • Added the package orderable addendum to the selective disclosure data sheet Go