SNVU663A June   2019  – May 2021 LP87524-Q1 , LP87524B-Q1 , LP87524J-Q1 , LP87524P-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Setup
    1. 2.1 SCL/SDA Pins
    2. 2.2 NRST Pin
    3. 2.3 ENx (GPIOx) Pins
    4. 2.4 nINT
  4. 3Configuration
    1. 3.1 Default OTP Configurations
      1. 3.1.1 LP87524B-Q1 OTP Configuration
        1. 3.1.1.1 Startup and Shutdown Sequence
      2. 3.1.2 LP87524J-Q1 OTP Configuration
        1. 3.1.2.1 Startup and Shutdown Sequence
      3. 3.1.3 LP87524P-Q1 OTP Configuration
        1. 3.1.3.1 Startup and Shutdown Sequence
  5. 4References
  6. 5Revision History

Setup

There are a few important connections to ensure the LP87524B/J/P-Q1 is configured correctly, each of which are described in this section. Good examples of how to connect the radar devices to the LP87524B/J/P-Q1 PMICs are shown in Figure 2-1, Figure 2-2 and Figure 2-3. LDOs are not required as the device meets noise and ripple specifications with LC filters. Refer to XWR1xxx Power Management Optimizations – Low Cost LC Filter Solution application report.

GUID-20210519-CA0I-ZFJZ-2K8T-TB9ZZZWZWKTP-low.svg Figure 2-1 Typical Connection to LP87524B-Q1
GUID-5FDB3BBA-0039-4F31-A991-A23805E08F86-low.gif Figure 2-2 Typical Connection to LP87524J-Q1
GUID-089D1D10-0EAB-46FE-A746-3323D4CAECCD-low.gif Figure 2-3 Typical Connection to LP87524P-Q1