SPMA057D January   2018  – June 2022 TM4C1290NCPDT , TM4C1290NCPDT , TM4C1290NCZAD , TM4C1290NCZAD , TM4C1292NCPDT , TM4C1292NCPDT , TM4C1292NCZAD , TM4C1292NCZAD , TM4C1294KCPDT , TM4C1294KCPDT , TM4C1294NCPDT , TM4C1294NCPDT , TM4C1294NCZAD , TM4C1294NCZAD , TM4C1297NCZAD , TM4C1297NCZAD , TM4C1299KCZAD , TM4C1299KCZAD , TM4C1299NCZAD , TM4C1299NCZAD , TM4C129CNCPDT , TM4C129CNCPDT , TM4C129CNCZAD , TM4C129CNCZAD , TM4C129DNCPDT , TM4C129DNCPDT , TM4C129DNCZAD , TM4C129DNCZAD , TM4C129EKCPDT , TM4C129EKCPDT , TM4C129ENCPDT , TM4C129ENCPDT , TM4C129ENCZAD , TM4C129ENCZAD , TM4C129LNCZAD , TM4C129LNCZAD , TM4C129XKCZAD , TM4C129XKCZAD , TM4C129XNCZAD , TM4C129XNCZAD , TMP1826 , TMP1826 , TMP1827 , TMP1827

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction to 1-Wire
    1. 1.1 Bus Requirements
    2. 1.2 Powering
  4. 2Functional Description
    1. 2.1 Signaling on 1-Wire
    2. 2.2 Address Format of the 1-Wire Device
    3. 2.3 Typical Communication Flow on the 1-Wire Bus
  5. 3Functions Available in TivaWare for C Series for 1-Wire Module
  6. 4Enumeration
    1. 4.1 Legacy Search Algorithm
      1. 4.1.1 Steps of the 3-Bit Search Algorithm
    2. 4.2 Fast Search Algorithm
  7. 5Summary
  8. 6References
  9. 7Revision History

2.1 Signaling on 1-Wire

The four types of signaling that are possible on the data line are:

  • Reset Sequence with Reset Pulse and Answer to Reset (ATR): A reset pulse is used to put all the devices in a known state. Target devices confirm their presence by sending an ATR signal, which is done by holding the line low. The host controller samples the bus, and if the bus reads low, then at least one target device is present.
    Table 2-1 Reset Signaling Description and Implementation
    Operation Description Implementation
    Reset Reset the 1-Wire bus target devices and prepare them for a command. Drive the bus low for 480 µs to reset all the devices. The host then samples the bus for the next 240 µs while the target Answer to Reset (ATR).
    Figure 2-1 Reset Sequence Bus Timing When There is at Least 1 Device on the Bus
  • Write logic 0 onto the bus
    Table 2-2 Write Logic 0 Bit Signaling Description and Implementation
    Operation Description Implementation
    Write logic 0 Send 0 bit to the 1-Wire target devices Drive the bus low for 60 µs
    Figure 2-2 Write Logic 0 Bus Timing
  • Write logic 1 onto the bus
    Table 2-3 Write Logic 1 Signaling Description and Implementation
    Operation Description Implementation
    Write 1 bit Send 1 bit to the 1-Wire target devices Drive the bus low for < 15 µs. Typical times are about 6 µs. Release the bus until 60 µs after the falling edge.
    Figure 2-3 Write Logic 1 Bus Timing
  • Read bit: Reads one bit from the target devices. Read bit signaling is similar to write “1” signaling, except that the host controller reads instead of writes.
    Table 2-4 Read Bit Signaling Description and Implementation
    Operation Description Implementation
    Read bit Read a bit from the 1-Wire target device Drive the bus low from 1 µs to 15 µs. Sample the bus at 15 µs after the falling edge to read the bit from the target device.
    Figure 2-4 Read Logic 1 Bus Timing
    Figure 2-5 Read Logic 0 Bus Timing