SPRACH6E January   2019  – May 2024 66AK2G12 , AM2431 , AM2432 , AM2434 , AM3356 , AM3357 , AM3358 , AM3359 , AM4376 , AM4377 , AM4378 , AM4379 , AM5706 , AM5708 , AM5716 , AM5718 , AM5726 , AM5728 , AM5729 , AM5746 , AM5748 , AM5749 , AM6411 , AM6412 , AM6421 , AM6441 , AM6442 , AMIC110 , AMIC120

 

  1.   1
  2.   Industrial Communication Protocols Supported on Sitara™ Processors and MCUs
  3.   Trademarks
  4. 1Introduction
  5. 2Communication Protocols
    1. 2.1 PROFINET
    2. 2.2 EtherCAT
    3. 2.3 EtherNet/IP
    4. 2.4 IO-Link
    5. 2.5 Simple Open Real-Time Ethernet (SORTE)
    6. 2.6 Parallel Redundancy Protocol (PRP)
    7. 2.7 High-Availability Seamless Redundancy (HSR)
    8. 2.8 OPC UA
    9. 2.9 Modbus TCP/IP
  6. 3Position Encoders
    1. 3.1 EnDat 2.2
    2. 3.2 HIPERFACE DSL
    3. 3.3 Tamagawa
    4. 3.4 BiSS- C
  7. 4Sitara Support for 3rd Party Protocol Stacks
  8.   Revision History

3.2 HIPERFACE DSL

Sitara processors currently support HIPERFACE DSL®. Evaluation and production software is available MCU+ SDK. The supported features are listed below.

  • External pulse synchronization
  • Safe position
  • Supports up to 100m cable
  • Communication status
  • Register interface to be compatible with SICK HDSL FPGA IP Core. (except registers that have different functionality for read and write)
  • Parameter channel communication (short message write)