SPRACP5 December 2019 TMS320F2802-Q1 , TMS320F28020 , TMS320F280200 , TMS320F28021 , TMS320F28022 , TMS320F28022-Q1 , TMS320F280220 , TMS320F28023 , TMS320F28023-Q1 , TMS320F280230 , TMS320F28026 , TMS320F28026-Q1 , TMS320F28026F , TMS320F28027 , TMS320F28027-Q1 , TMS320F280270 , TMS320F28027F , TMS320F28027F-Q1 , TMS320F28030 , TMS320F28030-Q1 , TMS320F28031 , TMS320F28031-Q1 , TMS320F28032 , TMS320F28032-Q1 , TMS320F28033 , TMS320F28033-Q1 , TMS320F28034 , TMS320F28034-Q1 , TMS320F28035 , TMS320F28035-EP , TMS320F28035-Q1 , TMS320F28050 , TMS320F28051 , TMS320F28052 , TMS320F28052-Q1 , TMS320F28052F , TMS320F28052F-Q1 , TMS320F28052M , TMS320F28052M-Q1 , TMS320F28053 , TMS320F28054 , TMS320F28054-Q1 , TMS320F28054F , TMS320F28054F-Q1 , TMS320F28054M , TMS320F28054M-Q1 , TMS320F28055 , TMS320F2806-Q1 , TMS320F28062 , TMS320F28062-Q1 , TMS320F28062F , TMS320F28062F-Q1 , TMS320F28063 , TMS320F28064 , TMS320F28065 , TMS320F28066 , TMS320F28066-Q1 , TMS320F28067 , TMS320F28067-Q1 , TMS320F28068F , TMS320F28068M , TMS320F28069 , TMS320F28069-Q1 , TMS320F28069F , TMS320F28069F-Q1 , TMS320F28069M , TMS320F28069M-Q1
Analog-to-Digital Converters (ADCs) are an important part of the C2000 Microcontroller (MCU) devices. In embedded processing, the conversion of a real time signal into a digital reading is essential for many real-time applications. Often, choosing the correct setup and configuration for an ADC can be difficult depending on system requirements. This application report discusses configuration settings, specifically the acquisition sample and hold time (ACQPS), with a focus on the F2803x device family. Some insight is given into which ACQPS values should be avoided based on the internal structure of a type 3 ADC in order to maximize the ADC’s performance by minimizing offset/gain error and achieving better integral and differential linearity. To achieve these results, this document follows a methodical approach first going through error internal to the ADC itself then the error based on ADC performance specifications. The information provided in this application report is applicable to all C2000 devices with a type 3 ADC.
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The sample and hold time, otherwise known as the ‘sample window’ time, is the amount of time allotted to charging the internal sampling capacitor of an ADC. Some applications may require a longer or shorter time depending on the drive strength of the external connections along the signal path to the ADC pin. For the F2803x device, the acquisition sample and hold (S+H) window size is configured in the ADCSOCxCTL register, and set to a value represented by one less than the desired number of ADC clock cycles. For example, an ACQPS value set to 28 would indicate 29 ADC clock cycles. Since this value is in terms of ADC clock cycles, it is dependent on the ADC's operational frequency. The F2803x devices have two ADC frequency settings, SYSCLK and SYSCLK/2, configurable through the CLKDIV2EN bit field in the ADCCTL2 register. This usually translates to 60 MHz and 30 MHz, respectively. The conversion time is always 13 ADC clock cycles. Therefore, the total time to process a single conversion of an analog voltage is the sample time plus the conversion time. For specific examples on finding the total processing time, see the TMS320F2803x Technical Reference Manual (TRM).
A smaller ACQPS value allows for more ADC readings within a given time frame in comparison to a larger ACQPS value. However, choosing a smaller ACQPS value may not allow the settling time of the sampling capacitor to stabilize, possibly leading to inaccurate results. Having an insufficient ACQPS value could also lead to cross-talk within sequential readings. Therefore, choosing the correct ACQPS value for a given system design is an important decision. Included in the TRM is a generalized list of non-valid ACQPS values. These values lead to significant variation from the specifications defined in the TMS320F2803x Microcontrollers Data Sheet for ADC performance. Table 1 expands on information provided by the TRM to list valid ACQPS values based on the data acquired in this analysis; these values are optimal ACQPS values that lead to stable ADC operation under all conditions and whose conversion results meet data sheet specifications. Values referred to as non-valid throughout this document are those which fall outside the valid ranges.
Frequency (MHz) | Overlap Mode | Non-Overlap Mode |
---|---|---|
≤ 30 | {6-63} | {6-63} |
> 30 & < 60 | {7-11, 21-24, 34-36, 47-50, 60-63} | {7-16, 21-29, 34-42, 47-55, 60-63} |
60 | {6-10, 12-14, 20-23, 25-27, 33-36, 38-40, 46-49, 51-53, 59-62} | {6-16, 18-29, 31-42, 44-45, 57-63} |
The ADC can operate in overlap mode. In this mode, ADC conversions occur at the same time a new voltage is being sampled. By comparison, in non-overlap mode the sample and conversion of the input signal occur sequentially. Since the ACQPS value determines the amount of acquisition and hold time, the distinction between overlap and non-overlap mode impacts the amount of conversions the ADC performs within an application. Thus, this report will analyze both modes independently from one another.
In order to bound the effect of the S+H time on the ADC’s performance, the data sheet minimum, typical, and maximum conditions for operational temperature and analog voltage (VDDA) are discussed within this report in conjunction with the ACQPS setting. Intermediate values of these parameters can be assumed to follow similar trends, but require in-depth analysis for specific system conditions. Efforts were made to ensure the data presented had adequate code spread. For more information regarding this topic, see Section ASection A.1.
NOTE
All values referenced from the TMS320F2803x Microcontrollers Data Sheet are taken from the time this report was publicized.
The offset error of an ADC can be defined as the deviation between the measured and ideal reading, in terms of Least Significant Bits (LSBs), when a 0 volt (V) input is applied to any of the input pins. Usually offset error is adjusted for by correcting it through the OFFTRIM bits in the ADCOFFSETTRIM register. For more detailed information regarding the process of reducing offset error, see the ADC Zero Offset Calibration section in the TMS320F2803x Technical Reference Manual (TRM). Each ACQPS setting needs to be trimmed differently, as each of the values leads to a different offset error under the same system conditions. Also, each start of conversion (SOC) channel can be configured to have a different ACQPS setting. If this is done in an application, then each channel should be calibrated separately.
The data sheet specifies ± 20 LSBs of offset error after executing a single self-calibration and ± 4 LSBs for periodic self-recalibration. Figure 2 and Figure 3 show the variation of average offset error among different ACQPS values under nominal conditions with no calibration.
Specifically in overlap mode, there are certain ACQPS values that have worse offset error than others. Both in overlap and non-overlap mode, 60MHz can lead to larger negative offset errors particularity for non-valid ACQPS values. Errors from intermediate frequencies between 30 MHz and 60 MHz are not guaranteed to follow the same trends.
As the VDDA supply increases from the minimum supported value to the maximum, the offset error also increases, across non-valid ACQPS settings. The disparity between offset error as it correlates to frequency is also increased when the temperature is lowered to the minimum operational temperature. Therefore, the worst offset error is seen at the lowest operational temperature and the highest operational analog voltage.
As previously mentioned, the offset error can be corrected through calibration. Periodic self calibration is encouraged in order to reduce offset error due to fluctuations in temperature. For software examples on performing periodic self-calibration, or calibrating each SOC differently, see the ADC examples in C2000WARE.