2 Offset Error

The offset error of an ADC can be defined as the deviation between the measured and ideal reading, in terms of Least Significant Bits (LSBs), when a 0 volt (V) input is applied to any of the input pins. Usually offset error is adjusted for by correcting it through the OFFTRIM bits in the ADCOFFSETTRIM register. For more detailed information regarding the process of reducing offset error, see the ADC Zero Offset Calibration section in the TMS320F2803x Technical Reference Manual (TRM). Each ACQPS setting needs to be trimmed differently, as each of the values leads to a different offset error under the same system conditions. Also, each start of conversion (SOC) channel can be configured to have a different ACQPS setting. If this is done in an application, then each channel should be calibrated separately.

1. This graph demonstrates offset error for a 3-bit ADC. The same description applies to a 12-bit ADC. FS represents Full Scale.

Figure 1. Offset Error

1. Data presented in this figure was acquired under nominal operating conditions.

Figure 2. Offset Error vs. ACQPS in Overlap Mode

The data sheet specifies ± 20 LSBs of offset error after executing a single self-calibration and ± 4 LSBs for periodic self-recalibration. Figure 2 and Figure 3 show the variation of average offset error among different ACQPS values under nominal conditions with no calibration.

1. Data presented in this figure was acquired under nominal operating conditions.

Figure 3. Offset Error vs. ACQPS in Non-Overlap Mode

Specifically in overlap mode, there are certain ACQPS values that have worse offset error than others. Both in overlap and non-overlap mode, 60MHz can lead to larger negative offset errors particularity for non-valid ACQPS values. Errors from intermediate frequencies between 30 MHz and 60 MHz are not guaranteed to follow the same trends.

As the VDDA supply increases from the minimum supported value to the maximum, the offset error also increases, across non-valid ACQPS settings. The disparity between offset error as it correlates to frequency is also increased when the temperature is lowered to the minimum operational temperature. Therefore, the worst offset error is seen at the lowest operational temperature and the highest operational analog voltage.

As previously mentioned, the offset error can be corrected through calibration. Periodic self calibration is encouraged in order to reduce offset error due to fluctuations in temperature. For software examples on performing periodic self-calibration, or calibrating each SOC differently, see the ADC examples in C2000WARE.