All combinations of TX and RX delay values can be viewed as a 2 dimensional plot, with RX PDL Delay on the horizontal axis, and TX PDL Delay on the vertical axis. Figure 2-1is a stylized, representative plot showing typical TX, RX, and Read Delay configurations that will allow the OSPI PHY to read successfully. Colored areas show the TX and RX combinations for the different ref_clk targets that result in valid reads (passing region). White space represents TX and RX combinations in which valid data will not be read (failing regions).

The passing region is divided into two sub regions, each one corresponding to a target cycle. The OSPI tuning algorithm identifies the largest region, selects that corresponding ref_clk target, and sets the TX and RX PDL delays to sample within that ref_clk target.

TX min and max (side walls of the passing region) are formed by the setup and hold time requirement of the OSPI device. TX delays outside this range cause command and address bytes to be latched incorrectly by the OSPI device, resulting in an unsuccessful read.

RX min and max (top and bottom of the passing region) are formed by the setup and hold time requirement of OSPI Controller. RX delays outside this range cause data bytes to be latched incorrectly by the OSPI controller, resulting in an unsuccessful read.

Both the TX PDL Delay and RX PDL Delay contribute to the round trip delay, which pushes the sample point from one ref_clk cycle to the next. The diagonal line between sub regions exists because the sum of PDL delays must not exceed a fixed value in order to sample within the 1st Ref_Clk Target.