ADC Input Circuit Evaluation for C2000 MCUs (using TINA-TI simulation tool)
Abstract
The analog-to-digital converter (ADC) is a key module used to sense feedback and monitoring signals in a real-time control application. However, without careful design and evaluation of the circuits driving the ADC input, significant sample-and-hold circuit (S+H) settling errors can occur, resulting in poor performance of the ADC sensing and thus the system. This application report will identify the resources that can be used to understand ADC input settling and design appropriate ADC driving circuits as well as how to evaluate these resources in the specific context of TMS320F2837xD, TMS320F2837xS, TMS320F2838x, TMS320F2807x, TMS320F28004x, TMS320F28002x, TMS320F28003x, TMS320F280013x, and TMS320F280015x series microcontrollers.
Project collateral and source code discussed in this application report can be downloaded from the following URL: http://www.ti.com/lit/zip/spract6.
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1 Introduction
When designing a system utilizing C2000 real-time MCUs, evaluating the input circuits that are driving the ADC for proper settling is a necessary step. Inadequate settling can lead to a variety of sampling issues, most commonly signal distortion and memory-crosstalk. This application report explores the methodology presented in the seven-part video series on ADC input settling by TI precision labs: TI Precision Labs - SAR ADC Input Driver Design in the specific context of the ADCs on C2000 real-time MCUs.
1.1 Mechanism of ADC Input Settling
To convert a sensed analog voltage to a digital conversion result, the ADC first must accurately capture the applied input voltage into its sample-and-hold circuit (S+H). As shown in Figure 1-1, this entails charging the internal ADC S+H capacitor (Ch) to within some acceptable tolerance (typically 0.5 LSBs) of the applied voltage within the configured acquisition window time (also referred to as the S+H time).
Figure 1-1 Settling of the ADC S+H
CapacitorQuickly charging Ch to the applied voltage is complicated by the finite bandwidth and settling time of the external ADC driver circuit and of the settling time of the internal ADC S+H circuit. In Figure 1-1, the driver is show as an op-amp (OPA320), which has a finite bandwidth, and the driver circuit also has intentionally placed source resistance (Rs) and intentionally placed source capacitance (Cs) which have a finite settling time determined by their RC time constant. Note that other circuit topologies are possible for driving the ADC, and these circuits may have additional components that need to be modeled to ensure appropriate settling time. These components could include unintentional parasitics such as the output impedance of a sensor or the effective source resistance of a voltage divider. Figure 1-1 also shows that the ADC has an internal parasitic switch resistance (Ron). This, along with Ch, provides an additional RC time constant that limits settling speed.
