1 Introduction

When driving an ADC input, achieving good settling performance is critical. Failing to achieve the necessary settling performance in the ADC driving circuits can result in distortion and memory cross-talk in the ADC conversion results. For an in depth discussion of the importance of minimizing errors associated with ADC input settling, see Appendix A. The signal conditioning circuits used to drive an ADC channel can vary widely in their requirements and implementation depending on the application requirements for that particular channel as well as the ADC input and sampling characteristics.

When sampling a high bandwidth signal near the maximum sample rate in a high-speed ADC, a very high performance driving circuit is required. This typically is comprised of a high-speed and low-noise op-amp stage that has passive component values optimized for minimal settling time (low resistor and capacitor values). These high performance drive stage circuits are suitable for driving most input signals, but require a high bandwidth op-amp which can have high component cost and may consume substantial printed circuit board area. Furthermore, if significant low-pass filtering is desired (many times desirable to limit noise in the conversion results), an additional active op-amp based filter stage may be necessary, adding cost and area.

Under certain circumstances, signals with sufficiently low sample rate can be directly interfaced to an ADC input channel by using a large "charge-sharing" capacitor placed on the ADC input. This method has the advantage of being simple, low-cost, and provides low-pass filtering. Furthermore, this can sometimes reduce sampling latency associated with the ADC acquisition. In particular, real-time control applications tend to use the ADC to scan through multiple multiplexed channels in a burst of conversions. These periodic bursts result in a sample rate on each channel that can be much less than the maximum sample rate of the ADC, which can sometimes achieve the necessary conditions for a charge-sharing input design.

This application report explains the mechanism that charge-sharing inputs use to achieve fast settling and will provide methods for designing a charge-sharing ADC driving circuit. Simulation methods will also be provided for verifying proper circuit settling behavior.