In the system presented in Section 3.1, two ADCs are used to sample four voltages, only one of which is specified to have poor input settling performance (voltage V2). Allocating two signals to each of the two ADCs results in the shortest overall latency to process the four voltages. However, if the sampling scheme is rearranged as shown in Figure 4-1, then the signal with poor settling performance (voltage V2) receives a dedicated ADC.

The main benefit of isolating the affected signal onto a single ADC is that the memory cross-talk error now originates from the previously sampled value of the same signal. If the signal is not moving very fast, the S+H circuit will start with a value close to the current input voltage. This greatly reduces the distance the input has to settle, resulting in acceptable settling performance. However, if the input experiences a large step in the input voltage, it may take several samples for the ADC to catch up with the new value on the input. Thus, a dedicated ADC strategy is generally more appropriate for slow moving or DC input signals. However, even in the case of faster signals, the memory cross-talk effect at least becomes systematic, which is usually an improvement compared with a memory error coupling into the signal in question from an unrelated signal.

Of course, dedicating an ADC to sample a single input signal results in increased latency in processing the remaining signals in the application. For instance, after re-arranging the signals as shown in Figure 4-1, the latency to produce the final ADC result has increased by 50%! (assuming all conversions are configured to take the ADC equal amounts of time to process).