6 Summary

Failing to design ADC input driving circuits in a real-time control application for proper S+H settling performance can lead to a variety of performance issues. Primary among these issues is memory cross-talk: an error where a sampled signal is affected by the previously sampled channel in the ADC sampling sequence. While the best course of action when this issue is discovered is to re-design the hardware circuits to achieve good settling performance, this may not always be feasible due to aggressive design constraints or working with an existing design that can't be significantly modified. In cases where hardware re-design is not viable, modifying the sampling sequence to move the affected channel to a dedicated ADC, or restructuring the sequence to sample VREFLO before the affected channel are possible options to help mitigate the memory cross-talk error.

The dedicated ADC method is simple and can use the minimum S+H duration to sample the channel of interest. However, this method may not be suitable for higher bandwidth signal and there will likely not be sufficient hardware resources to support many signals utilizing this method.

Adding a sample of VREFLO (0V) before the channel of interest is also a simple and convenient strategy to transform the memory cross-talk into a more deterministic form. It can be used for higher speed signals than the dedicated ADC method, but may not be able to use the minimum S+H duration. This method produces a significant amount of gain error, but this error can be easily calibrated out of the ADC results via an additional gain compensation scheme.