To convert a sensed analog voltage to a digital conversion result, the ADC first must accurately capture the applied input voltage into its sample-and-hold circuit (S+H). As shown in Figure 2-1, this entails charging the internal ADC S+H capacitor (C_h) to within some acceptable tolerance (typically 0.5 LSBs) of the applied voltage within the configured acquisition window time (also referred to as the S+H time).

Figure 2-1 Settling of the ADC S+H Capacitor

Quickly charging C_h to the applied voltage is complicated by the finite bandwidth and settling time of the external ADC driver circuit and of the settling time of the internal ADC S+H circuit. In Figure 2-1, the driver is show as an op-amp (OPA320), which has a finite bandwidth, and the driver circuit also has intentionally placed source resistance (R_s) and intentionally placed source capacitance (Cs) which have a finite settling time determined by their RC time constant. Note that other circuit topologies are possible for driving the ADC, and these circuits may have additional components that need to be modeled to ensure appropriate settling time. These components could include unintentional parasitics such as the output impedance of a sensor or the effective source resistance of a voltage divider. Figure 2-1 also shows that the ADC has an internal parasitic switch resistance (R_on). This, along with C_h, provides an additional RC time constant that limits settling speed.