In Section 3.1, an example system that sampled four voltages was presented. One of these voltages, V2, was specified to have poor settling performance (due to excessively high source impedance from using a voltage divider to drive the ADC input directly). Figure 5-1 shows one possible re-organization of the sampling scheme where a sample of VREFLO (zero-scale) has been added before the channel in question. The result of this is to replace memory cross-talk from voltage V1 (which is an independent signal that could take on any voltage at any time) with memory cross-talk from VREFLO (that reliably produces cross-talk that pulls V2 towards exactly 0 V).

Unlike the single-ADC method, it is possible to apply the pre-sampling VREFLO methodology to multiple signals on the same ADC. This method is only limited by the number spare start-of-conversion (SOC) structures available in the ADC wrapper to sequence the extra conversions (no external pins are needed) and the amount of additional latency spent processing the VREFLO samples that the application can tolerate. Later sections will also show that a light post-processing of the ADC results is also desirable. Performing this operation will add some additional latency that will also need to be absorbed by the application.