//----------------------------------------------------------------------
    // CMPSS5H Capture ZVS (Inductor current NZC)
    //----------------------------------------------------------------------
    //setup analog input of CMPSS 5, connect inductor current signal to CMPSS5
    ASysCtl_selectCMPHPMux(ASYSCTL_CMPHPMUX_SELECT_5, 2);
    // Power up Comparator locally
    CMPSS_enableModule(base5);
    // Connect the inverting input to internal DAC. Invert CMPH output.
    CMPSS_configHighComparator(base5, CMPSS_INSRC_DAC|CMPSS_INV_INVERTED);
    // Set DAC output
    CMPSS_setDACValueHigh(base5, (int16_t)(iL_limit));
    // DACHVALA is updated from DACHVALS (no Internal ramp)
    CMPSS_configDAC(base5, CMPSS_DACSRC_SHDW);
    // Output = asynch comparator output (output inverted)
    CMPSS_configOutputsHigh(base5, CMPSS_TRIP_ASYNC_COMP);
    // Xbar setting
    //------------------------------------------------------------------------
    // CMPSS5H – ZVS (Inductor current NZC)
    //------------------------------------------------------------------------
    XBAR_setEPWMMuxConfig(XBAR_TRIP5, ZVS_CAPTURE_XBAR_MUX_CONFIG);
    XBAR_enableEPWMMux(XBAR_TRIP5, ZVS_CAPTURE_XBAR_MUX);    
    //Clear XBAR flag during initialization
    XBAR_clearInputFlag(XBAR_INPUT_FLG_CMPSS2_CTRIPH);
    //***********************************************************************************
    // Configure PWM1A for switching Frequency and valley switching.
    //***********************************************************************************
    // ZVS(Inductor current NZC) related registers setup starts here
    // Select one of the DCAEVT1 events as input to the event filtering logic block
    EPWM_setDigitalCompareFilterInput(base1, EPWM_DC_WINDOW_SOURCE_DCAEVT1);
    // Edge filter is selected
    EPWM_enableDigitalCompareEdgeFilter(base1);
    // Edge mode is selected
    EPWM_setDigitalCompareEdgeFilterMode(base1, EPWM_DC_EDGEFILT_MODE_BOTH);
    // Edge count is selected
    EPWM_setDigitalCompareEdgeFilterEdgeCount(base1,1);
    //Software trigger (triggered in ISR)
    EPWM_setValleyTriggerSource(base1, EPWM_VALLEY_TRIGGER_EVENT_SOFTWARE);
    //valley capture enabled
    EPWM_enableValleyCapture(base1);
    //DELAY applied
    EPWM_enableValleyHWDelay(base1);
    //SW DELAY duration
    EPWM_setValleySWDelayValue(base1, SWDELAY);
    // DCAH = Comparator 5 output = TRIP5in
    EPWM_selectDigitalCompareTripInput(base1, EPWM_DC_TRIP_TRIPIN5,EPWM_DC_TYPE_DCAH);
    //DCAH = high (1 TBCLK wide pulse is generated by edge filter)
    EPWM_setTripZoneDigitalCompareEventCondition(base1, EPWM_TZ_DC_OUTPUT_A1,
                                                 EPWM_TZ_EVENT_DCXH_HIGH);
    //Source is filtered DCAEVT1
    EPWM_setDigitalCompareEventSource(base1, EPWM_DC_MODULE_A, EPWM_DC_EVENT_1,
                                      EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);
    //Async
    EPWM_setDigitalCompareEventSyncMode(base1, EPWM_DC_MODULE_A, EPWM_DC_EVENT_1,
                                        EPWM_DC_EVENT_INPUT_NOT_SYNCED);
    //Use blanking window to filtering PZC edge and noise
    EPWM_enableDigitalCompareBlankingWindow(base1);
    EPWM_setDigitalCompareBlankingEvent(base1, EPWM_DC_WINDOW_START_TBCTR_ZERO);
    // Blanking Window Offset = CMPA(n+1)
    EPWM_setDigitalCompareWindowOffset(base1, 1);
    // Blanking window length
    EPWM_setDigitalCompareWindowLength(base1, MIN_PERIOD);
    // Enable time-base counter capture
    EPWM_enableDigitalCompareCounterCapture(base1);
    //ZVS code stops here