SPRADE9 November   2023 AM2431 , AM2432 , AM2434 , AM623 , AM625 , AM625-Q1 , AM625SIP , AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62P-Q1 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442 , AM6526 , AM6528 , AM6546 , AM6548 , AM67 , AM67A , AM68 , AM68A , AM69 , AM69A , DRA821U , DRA821U-Q1 , DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Industrial Ethernet Protocol Software Stack
    1. 2.1 Overview
    2. 2.2 EtherCAT
  6. 3Evaluation Platform and Methods
    1. 3.1 Hardware
    2. 3.2 Software Platform
    3. 3.3 Test Application
    4. 3.4 Test Topology
  7. 4Results
    1. 4.1 Time Synchronization
    2. 4.2 Transmit Timing
  8. 5Summary
  9. 6References

EtherCAT

EtherCAT is an IEEE 802.3 Ethernet-based fieldbus system standardized in International Electrotechnical Commission (IEC 61158). The technology is supported by the EtherCAT Technology Group, an international community of users and vendors. The protocol is particularly popular in motion and motor control. The primary advantage of EtherCAT is that it supports automation applications that require short data-update times with low communication jitter. In the EtherCAT protocol, the EtherCAT Main (formerly called Master) sends a frame that passes through each Subordinate node (formerly called Slave). Each EtherCAT Subordinate device reads the data that is addressed to it as soon as the data is detected. Then, the subordinate device inserts the data into the frame, while the frame is on-the-fly bridged. The last Subordinate node in a segment (or branch) detects an open port and sends the message back to the main. The EtherCAT Main is the only node within a segment that actively sends a new EtherCAT frame. This capability permits the network to achieve over 90% of the available network bandwidth while preventing unpredictable delays, and thus guarantees real-time system response. EtherCAT is transported with EtherType identifier (0x88A4).

The only frames sent on the LAN are from the EtherCAT Main and the last Subordinate. The typical optimization at the Main is to have the stack directly access the Ethernet MAC controller, bypassing not only the networking stack, as with OPC UA Pub-Sub over raw Ethernet, but also bypassing the Ethernet driver to directly or natively own the entire Ethernet peripheral. Acontis [6] and IBV [7] are stack providers offering this optimization. An example of this is show in Figure 2-4.

GUID-20231011-SS0I-SDCK-PBMN-TSMFCNMF3KKZ-low.png Figure 2-4 EtherCAT Main Software Architecture [6]

EtherCAT is a broadly deployed protocol and detailed benchmarks are available on many platforms [8] [9] [10]. As a reference point of what can be achieved, the clock synchronization reached is usually claimed to be below 100 ns and in practice, ±20ns. Clock synchronization is usually measured by using an oscilloscope to view the required SYNC output on each Subordinate node and comparing the offset and jitter among each measurement. The SYNC output is logically similar to generating a 1 pulse per second (pps) type pin toggle from TSN time synchronization (IEEE 802.1AS). Figure 2-5 is an example of this measurement.

GUID-20231011-SS0I-HQ6S-JHKP-HS3XXVMXNVTS-low.png Figure 2-5 EtherCAT Time Synchronization Measurement Example [10]

For the second key timing metric, the ability to place an Ethernet frame precisely on the wire, some Ethernet MACs in embedded processors, like Texas Instruments Sitara™, and network interface cards (NICs) like Intel i210, added a non-IEEE feature called time triggered send (TTS). This feature allows placing an Ethernet frame precisely on the wire at a point of time, commonly applied to be exactly at the beginning of a communication cycle. With 100 Mbit/s (typical EtherCAT deployed today), this reaches +-40ns accuracy [5].