The main purpose of flash verification is to check whether the code and data in the flash memory are consistent with the initial content. Traditionally, flash verification is achieved through CRC. The flash memory blocks are sequentially calculated for CRC, and the calculated CRC is stored as the Golden CRC array. During power-on and periodic cyclic verifications, the flash memory blocks are sequentially calculated for CRC again, and the results are compared with the corresponding Golden CRC. If the results match, the verification passes. The problem with this verification method is that global interrupts still need to be disabled during flash verification, so the size of each memory block for a single detection needs to not be too large to avoid affecting the execution of system functional interrupts. With the increasing functionality of appliances and the gradual increase in the size of flash memory of the MCU, the time required for one round of flash self-test can become too long to meet the security requirements of certification organizations. Therefore, when using CRC to verify flash memory, it is necessary to balance the size of each memory block for a single detection and the time required for one round of self-checking. Figure 4-7 shows the flash CRC test structure. Flash CRC test is found in the test_application project called STA_FLASH_CRC, and the source code is in f280013x\source\stl_crc.c.

Figure 4-7 Flash CRC Test Structure

In the third-generation C2000 MCU recommended by TI for appliance applications, the flash memory comes with ECC verification functionality, which greatly reduces the time required for flash verification. When the flash memory is programmed, ECC codes are generated and stored in the corresponding memory locations. When the flash memory is read, the ECC module performs ECC calculation again and compares the results with the ECC generated during programming. This can detect single-bit errors and double-bit errors, with single-bit errors being correctable.

The on-chip flash memory is supported by single-error correction, double-error detection (SECDED) error correcting code (ECC) diagnostic. In this SECDED scheme, an 8-bit code word is used to store the ECC of 64-bit data and the corresponding address. The ECC decoding logic at the flash bank output checks the correctness of memory content. ECC evaluation is done on every data and program read. The data and program interconnects that connect the CPU and flash memory is not protected by ECC. Detected correctable errors can be corrected or not corrected, depending on whether correction functionality is enabled. Single-bit address ECC errors are flagged as uncorrectable errors. Errors that cannot be corrected generate an NMI and the ERRORSTS pin is asserted. Count of the corrected errors (single-bit data errors) is monitored by the flash wrapper and an interrupt is generated once the count exceeds the programmed threshold. The corrupted memory address of the last error location is also logged in the flash wrapper.

It is possible to test the functionality of ECC by injecting single-bit and double-bit errors in test mode and performing reads on locations with ECC errors, and checking for the error response. Flash ECC logic is checked with the help of ECC test registers (FECC_CTRL, FADDR_TEST, FECC_TEST, FDATAH_TEST, FDATAL_TEST). Correct functioning of error counter and threshold interrupt associated with single-bit errors can also be verified using this technique. Figure 4-8 shows the flash ECC test structure. Flash ECC test is found in the example\sdl_ex_flash_ecc_test project, and the source code is in f280013x\examples\sdl_ex_flash_ecc_test\sdl_ex_flash_ecc_test.c.

Figure 4-8 Flash ECC Test Structure