SPRUJ17H March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
The GF2M engine performs add, multiply and "divide-by-2" operations on binary field values. The binary field values are represented as bit strings that represent a polynomial with coefficients that are either 0 or 1.
Table 7-108 provides an overview of the operations supported by the GF2m Engine.
Command | Mathematical Operation | Description(1) | Number of Clock Cycles | Polynomial Register Content(2) | Reference |
---|---|---|---|---|---|
CLR | 0 -> tgt | Clear tgt operand register over its full bit length. Pointer tgt can be operand registers A, B, C or D. | 1 | Not used | Section 7.3.4.4.1.6.1 |
COPY | src0 -> tgt | Copy src0 operand to tgt operand register. Pointers src0 and tgt can be operand registers A, B, C or D. | 1 | Not used | Section 7.3.4.4.1.6.2 |
ADD | src0 + src1 -> tgt | Bitwise XOR operation on operands src0 and src1, store result in tgt register. Pointers src0, src1 and tgt can be operand registers A, B, C or D. | 3 | Not used | Section 7.3.4.4.1.6.3 |
MUL | src0 × src1 -> tgt (mod p) | Multiply operands src0 and src1, store result in the tgt register. Pointers src0, src1 and tgt can be operand registers A, B, C or D. | 2 + [field size/mul_depth] | Prime polynomial p | Section 7.3.4.4.1.6.4 |
SXL | src0 /= 2n (mod p) src1 /= 2n (mod p) | Assist function for an ‘Inverse’ operation: Shift-right src0 until its LSB is 1b; return shift value and Shift-right src1 that is conditionally XORed with the polynomial Pointers src0,src1 can be operand registers A, B, C or D | 1 per src0/1 shift + 1 cycle, if an XOR needs to be performed before the src1 shift | Prime polynomial p | Section 7.3.4.4.1.6.5 |
DEGREE | - | Assist function for an ‘Inverse’ operation: Implicit operation that determines the MSB of the last read 32-bit operand or polynomial word; returns the MSB bit position within this word in status register. | 1 (implicitly performed during operand read out) | - | Section 7.3.4.4.1.6.6 |