TIDUF53 December   2023 DRV8210 , INA350 , MSPM0L1306

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Terminology
    2. 1.2 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 System Design Theory
      2. 2.2.2 Bridge Biasing
      3. 2.2.3 INA Stage
      4. 2.2.4 Filter Design
    3. 2.3 Highlighted Products
      1. 2.3.1 MCU-MSPM0L1306
      2. 2.3.2 OPA-LMV324A
      3. 2.3.3 LDO-TPS7A2433
      4. 2.3.4 INA350
      5. 2.3.5 DRV8210
      6. 2.3.6 ATL431LI
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
      1. 3.1.1 System Connection
    2. 3.2 Software Requirements
    3. 3.3 Running the Demonstration
    4. 3.4 Test Results
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematic
      2. 4.1.2 BOM
      3. 4.1.3 PCB Layout Recommendations
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  11. 5About the Author

2.3.1 MCU-MSPM0L1306

This device is selected as the system MCU and is the brain of the system. The device can perform the following actions:

  • Measure systolic, diastolic, and heart rate in measure mode
  • Send data and results serially for visualization

This MCU has a 32-MHz Arm® Cortex®-M0+ core, 64k flash, and 4k SRAM. The MCU is differentiated because of high-performance analog peripherals. The device includes one 12-bit 1.68-Msps SAR ADC with up to 11.1 typical ENOB and 71 dB SNR, as well as additional 128x hardware oversampling. This MCU includes two zero-drift, zero-crossover chopper operational amplifiers (OPA) with down to 0.5-µV/°C drift and 2-µVPP 1/f noise with chopping mode.

These devices also offer intelligent digital peripherals such as four 16-bit general purpose timers, one-windowed watchdog timer, and a variety of communication peripherals including two UARTs, one SPI, and two I2C interfaces.

The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. The run mode has a power consumption of 71 µA/MHz, 1 µA standby with SRAM and register fully retained, and shutdown mode with down to 61-nA current consumption with IO wakeup capabilities.

Figure 2-8 shows more of the MSPM0L1306 blocks.

GUID-20231204-SS0I-DDZM-KLCN-JJZFHRNBK7BL-low.svgFigure 2-8 MSPM0L1306 Functional Block Diagram