This document analyzes two methods to increase the drive current from integrated gate-driver ICs. The performance of both the methods is compared by building boards and testing them at various conditions. These circuits are discussed in further detail in subsequent sections.

The most common current-boosting method is the use of an NPN-PNP transistor pair. The gate-drive output from the integrated driver is applied as the base drive for this transistor pair. Figure 2-1 shows the schematic of such a current boost circuit using the isolated gate-driver ISO5852S.

Figure 2-1 High-Current Gate Driver Using ISO5852S and BJTs

Signal isolation for the PWM input from MCU is provided by the driver IC itself. The gate-driver IC provides an isolation of 5.7 kV_RMS and can source and sink 2.5 and 5 A of current, respectively. Power isolation is achieved by an isolated flyback power supply built around the LM5180 device, a primary side regulated flyback converter with integrated 100-V MOSFET. For input side to output side isolation, a flyback transformer from Wurth Elektronik (part no: 750344600) is used. The use of this controller allows this gate-driver circuit to be compatible with 24-, 15-, or 12-V auxiliary power supplies. The primary (MCU) side of the ISO5852S can either be powered using the MCU power supply itself (by depopulating U3 and connecting the MCU supply to 3V3_MCU input), or by a 5-V supply generated by a TLV70450 LDO from the auxiliary power source. The gate-drive power generated by the flyback power stage is suitable for both IGBTs and SiC MOSFETs, as it is has dual outputs of +20 V and –6 V. The RST and PWM signals are from the MCU – PWM is the drive signal and RST (active low) is used for resetting the gate driver after clearing a fault event due to the DESAT pin detecting a short circuit of the power switch. About 10-ns noise filtering is provided on the PWM input. The FLT and RDY signals are status indication signals back to the MCU – FLT indicating by active low a fault situation detected by the gate driver and RDY indicating by active high that the driver is ready to receive PWM input.

On the output side, the NPN and PNP totem pole stage does current amplification. The BJTs that were used for current amplification were PHPT60410NYX and PHPT60410PYX, with a 20-A peak current rating. Because of the use of transistors in the active region, the drive outputs will be reduced by 0.7 V–0.8 V from the power-supply rails. This is not a significant problem with such high drive voltages. Also, adding a resistor between the base and emitter of the external transistors will allow the output voltage to reach the rail voltages. The ISO5852S device has an internal Miller clamp capable of sinking 2.5 A, typical. This pin can also be configured to drive an external PNP transistor for an external clamp. Using an external clamp increases the effectiveness by positioning it much closer to the gate of the power switch. With a sufficiently high negative bias of –6 V, it is not essential to use the Miller clamp, but is included as additional safety and also for demonstration of current boosting of the Miller clamp output. The diodes in D4 protect the output transistors from overvoltage during transient situations.

The DESAT overcurrent protection function in ISO5852S is maintained in this gate driver without any change from the recommended sensing circuit. However, due to the current boosting on the output drive, the slow turn-off DESAT protection might not work well without some modification of the circuit. The R16 – C20 network will ensure that the drive current during a DESAT event will be diverted away from the base of Q2 for the required amount of turn-off time. The values of these components can be calculated using Equation 1 and Equation 2:

Equation 1.

where

• I is the value of the internal current source which is 130 mA
• T_off is the desired turn-off time
• V_P is the positive drive voltage
• V_N is the negative drive voltage

The value of R16 can be estimated using the inequality in Equation 2:

Equation 2.

An alternate scheme for drive current boosting is given in Figure 3-1. Two N-channel MOSFETs are used as current boosting devices. As they are operated as saturated switches, the drive current is only limited by the on-time resistance and hence can achieve much higher current levels.

Figure 3-1 High-Current Gate Driver Using LM5106 and MOSFETs

In this circuit, signal isolation is provided by a digital isolator (ISO7721). To drive the driver MOSFETs, a low-voltage half-bridge driver IC (LM5106) is used. The power supply is the same as the previous circuit. However, a couple more LDOs are required to power the secondary side of the digital isolator and the half-bridge driver. The secondary side of the digital isolator is referred to the –6-V negative drive supply. So to power this side, a 5-V supply referred to this level is needed. This is provided by a 5-V LDO connected to the secondary return. For the gate-drive voltage for the driver MOSFETs (and the half bridge driver), a voltage of around 10 V (referred to the negative drive supply) is needed. This is generated by another 5-V LDO referred to the secondary return. This gives a total of 11 V (5 V from the LDO and 6 V from the negative drive supply) referred to as the negative drive supply.

For half-bridge drivers, typically two PWMs are required – the main PWM for the upper MOSFET and a complementary PWM for the lower MOSFET. However, the LM5106 half-bridge driver can generate the complementary signal internally with a dead-time determined by a programming resistor. This saves the need to have the complementary signal generated by the MCU. However, the half-bridge driver will need a level-shifted drive voltage to address the upper MOSFET. In this circuit, this voltage is provided by a bootstrap circuit comprising of D4, C27 , and R3 under the assumption that there is sufficient on-time for the lower MOSFET to charge. With the component values used in this circuit, the typical charging time is under 1 µs. That means, for PWM inputs with less than 1-µs off-time, the bootstrap capacitor might not be able to charge to the full supply voltage. Also, for low PWM frequencies (below a few 100 Hz), the bootstrap capacitor will not be able to hold the charge for the entire cycle. If such conditions are expected to be present, it is recommended to use an additional isolated supply to power the high-side – this can easily be generated by adding one more winding on the flyback power supply used. This will allow even 100% duty cycle operation.

The upper-side MOSFET is switched in accordance with the PWM input, while the lower MOSFET is switched based on the complementary of the PWM input resulting in output drive with the same polarity as the input PWM. As the drive current can be as high as 100 A, sufficient decoupling is required on the positive and negative drive-supply rails. If needed, additional capacitors can be added externally. This high peak current-drive capability is not required for most power devices, but by utilizing FETs of this power level, thermal dissipation can be greatly reduced when driving with peak currents of 20 A or higher. The peak current can be limited by using the external gate resistor since too high a peak current can result in undesirable ringing at the gate and uncontrolled slew rates of the power switch.