Achieving GaN Products With Lifetime Reliability

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1 Introduction

For a new technology to be successful, it must be reliable in the customer application. Silicon power transistors are now regarded as reliable, but this was not always the case. Confidence in their reliability developed with longstanding experience, resulting in a well-accepted qualification methodology whereby reliability and quality are certified by running standardized tests and using reliability models for lifetime calculations. These tests were developed to accelerate failure mechanisms, with reliability engineering conducted to achieve the desired lifetime.

GaN transistors have now been known for 28 years⁽¹⁾. RF GaN FETs are now widely deployed in cellular base stations. Power GaN FETs are more recent, with development efforts starting in the early twenty first century. The power GaN industry does not have the luxury of time, so has invested considerable effort to accelerate reliability development. As a result, power GaN FETs are now considered reliable and are being deployed in both commercial and automotive products.

Figure 1-1 GaN reliability is validated by supplementing well-established standards with recent JEDEC JC-70 GaN guidelines to cover both component and power-supply level operation.

A key criterion is the reliable product operation for a broad range of customer applications under both normal and extreme use conditions. The traditional silicon approach, does not adequately address the switching conditions of power management, so we have built upon it. Our approach is shown in Figure 1-1, and consists of GaN-specific methodology to address switching reliability, conduct test, address failure modes, extrapolate lifetime, and ensure operation under extreme conditions such as lightning surge and short circuit.

The methodologies of Figure 1-1 result from several other aspects important for technology maturity. First is the formation of the JEDEC JC-70 committee on Wide Bandgap Power Electronic Conversion Semiconductors, with three GaN-specific guidelines already released: JEP173, JEP180, and JEP182. Second is the creation of a body of literature on failure mechanisms and their acceleration. Third is the thought leadership around a common approach for application reliability, a challenging topic. TI has played a leadership role in all these aspects. As a result, TI GaN products incorporate a well-developed methodology to validate and assure the reliability of GaN under all conditions of operation.

The objective of this white paper is to describe the progress and methodology by which TI GaN product reliability is assured and to show results that demonstrate lifetime reliability in application.

2 Background

The qualification standards in use for silicon were first published in the 1990’s. The popular JEDEC JESD47 standard⁽²⁾, “Stress-Test-Driven Qualification of Integrated Circuits” was first published in July 1995 and the Automotive Electronics Council (AEC) Q100⁽³⁾ was first published in June 1994. These standards specify many tests which may be classified into three categories: device, electrostatic discharge (ESD), and package. At the time, memory and logic were the predominant applications, and the accelerated bias tests were intended to achieve an electric-field equivalent lifetime. The switching transitions of power management applications were not specifically considered.

Traditional device qualification is run by using a 1000h test at a junction temperature of 125ºC or higher at the maximum operating voltage. Running at 125ºC is equivalent to about nine years of use at T_j = 55ºC using an assumed activation energy of 0.7 eV.

Many of the tests also require a large number of parts to obtain defectivity and failure in time (FIT) statistics. For further background on traditional silicon qualification, see references 4 and 5.

Although JEDEC specifies the need for dynamic testing, conditions are not prescribed due to the ever-evolving applications and material sets in our industry⁽⁶⁾. The field of power conversion illustrates the difficulties. There are many different topologies and numerous components with which the GaN FET interacts. Determining the lifetime of a GaN FET in a power converter is challenging for the following reasons. First, running acceleration studies could cause many non-GaN failures. Second, the applicability to different topologies would not be clear. Third, the energy usage of running the large number of power converters needed is large. It has therefore not been straightforward to assure product-level reliability in a broad sense. As a result, traditional reliability testing has not covered the switching conditions of power management.

The need for GaN-specific reliability validation arose because traditional silicon qualification methodology was not fully addressing application reliability for GaN products. During the early days, we observed that hard-switched transitions were causing overheating and occasional hard-failure. This finding is important because a broad class of power conversion applications are hard-switched. We developed a comprehensive methodology for qualifying the reliability of GaN products, described in references 4 and 5. The papers describe a common approach of validating the application reliability of GaN FETs for a broad class of applications.

Figure 2-1 Schematic of the test vehicle used for universal hard-switch reliability validation of TI GaN devices. Dynamic R_DS(ON) is measured using the clamped V_DS sampling circuit.

The common approach is enabled by use of the switching locus curve to represent the type of switching stress applied to the device, and thereby the failure mechanism exercised. The switching locus curve is the trajectory of the i_D-v_DS waveform during a switching cycle⁽⁷⁾. A test vehicle circuit with a hard-switching locus will therefore apply relevant stress for hard-switching applications⁽⁷⁾.

Our test vehicle circuit shown in Figure 2-1 and described in references 4 and 5, is a boost converter stage with the output tied to the input to conserve energy. It is a similar circuit to the double pulse tester (DPT) with a different control. We use it in continuous-pulse mode for providing accelerated hard-switching stress per JEP182⁽⁸⁾. A highly-reliable diode is used for the high-side device, eliminating high-side drive complexity. Its simplicity minimizes system-related failures, enabling accelerated testing for the desired failure mechanism. It is also designed to measure dynamic R_DS(ON) per JEP173⁽⁹⁾.

Traditional silicon qualification testing alone is not a guarantee for reliable application performance because it does not include hard-switching transitions, nor does it test for dynamic R_DS(ON). Both aspects are very important for the proper operation of all devices in hard-switching applications. We have seen that GaN devices from processes that pass traditional silicon qualification can still overheat and show a decrease in efficiency when run in a in a hard-switched application. However, parts run reliably if the process passes traditional qualification testing plus hard-switching reliability testing⁽¹⁰⁾.

It is often asked whether a device that is robust to hard-switching is also robust for soft-switching applications. This is reasonable thinking because hard-switching creates more hot electrons, which can increase electron trapping and result in higher dynamic R_DS(ON)⁽¹¹⁾. It was previously shown⁽¹⁰⁾ that hard-switching is the more stressful case for TI GaN devices. However, there have been recent literature reports⁽¹²⁾ that soft-switching can cause higher dynamic R_DS(ON) for some types of devices. Our stress testing confirms that TI GaN devices are reliable for both hard and soft-switching applications and confirms that soft-switching does not cause higher dynamic R_DS(ON) for GaN technology in general.

3 Addressing GaN Failure Mechanisms

Failure mechanisms are present in all devices. Reliability engineering consists of making devices robust to failure mechanisms and their resulting failure modes. For GaN devices, the major failure modes are the increase of leakage currents and changes in parameters such as on-resistance. These can result in a reduction in efficiency or in circuit malfunction. Hard-failure can also occur.

In GaN devices, the primary failure mechanisms are Time Dependent Breakdown (TDB), hot-carrier degradation, and charge trapping. Time Dependent Breakdown is a well-known phenomenon⁽¹³⁾ in dielectrics used in silicon processing, and its modeling is treated in JEDEC publications⁽¹⁴⁾. It occurs due to high electric-field and is responsible for increased leakage currents and can lead to hard-failure. Hot-carrier degradation is also well-known in Si MOSFETs, where hot-carrier stress causes defect generation. Hot-carriers are created by hard-switching in power FETs, and have been seen to result in both charge trapping and wearout in GaN
FETs^{(5, 15)}.

GaN FETs operate with high electric fields in several regions, as shown in Figure 3-1. TI GaN FETs have been engineered for TDB lifetime with the use of special test structures for each of these high-field regions. A model has been built incorporating 1.8 million device hours of testing and shows a low FIT rate of 0.8 FIT with 10 years of continuous application of 480 V and 125°C for the LMG3410R070 product.

Figure 3-1 Schematic cross-section of the GaN device showing the high-field regions in the device.

Charge trapping is also a well-known phenomenon in semiconductor devices, and can cause parametric shifts. An important consequence of charge trapping in GaN devices is a shift in the on-resistance, R_DS(ON)⁽¹⁶⁾. Negative trapped charge repels channel electrons, thereby resulting in fewer electrons in the channel, as shown in Figure 3-2. R_DS(ON) increases because the number of electrons in a portion of the channel layer is reduced. Charge can be trapped in the buffer layer, in dielectrics, and at interfaces. Charge trapping can occur due to high drain voltage when the device is off, or from hot electrons when switching. The R_DS(ON) inclusive of charge trapping effects is called dynamic R_DS(ON). The dynamic nature arises because R_DS(ON) recovers as the trapped charge dissipates or detraps. It is therefore important to evaluate dynamic R_DS(ON) at the timescales of switching cycles. A consequence is that if the detrapping or device on-time is low, there could be more charge buildup. Dynamic R_DS(ON) evaluation at low duty cycle is therefore a good method to validate material quality.

Power devices need to be engineered for stable R_DS(ON), since they are continually subject to high voltage and hot electron generation while switching. Increases in R_DS(ON), will decrease efficiency through higher conduction loss. Furthermore, the trap density can increase as the device ages. It is therefore important for dynamic R_DS(ON) to be stable with aging, to prevent excessive self-heating and premature failure.

Figure 3-2 Schematic cross-section of a GaN device shows how trapped electrons can increase R_DS(ON) by reducing the number of electrons in the channel layer

TI GaN products have been engineered for stable dynamic R_DS(ON) with aging. This was achieved through years of in-house material and process engineering. It included ways of growing high-quality GaN crystal, optimizing the dielectric films, and achieving very clean interfaces. We validate dynamic R_DS(ON) lifetime stability by using the test vehicle in Figure 2-1. This is one of the circuits listed in JEP182 for the continuous-switching evaluation of GaN power conversion devices. Hard-switching stress is applied per JEP180 at a current corresponding to the maximum power condition, the maximum recommended V_DS and worst-case junction temperature, for 1000h. Dynamic R_DS(ON) stability with aging is validated through low duty-cycle hard-switching stress. Dynamic R_DS(ON) aging data from products in the LMG34xx family is shown in Figure 3-3. The duty cycle used was about 0.5%, which provides excellent ability to discriminate material quality. Dynamic R_DS(ON) measurement is conducted per JEP173. The high stability of dynamic R_DS(ON) under very low duty cycle for best-practice lifetime stress conditions attests to excellent aging of the material: it demonstrates the lack of new trap creation with aging and validates the long-term stability of dynamic R_DS(ON) under all conditions of operation. To assure manufacturability of material with this quality, we have had a coordinated program to develop in-line electrical tests that are predictive of dynamic R_DS(ON) in application. The excellent dynamic R_DS(ON) stability of our production material has also been verified by others⁽¹⁶⁾.

The reason that low duty cycle provides excellent sensitivity to charge trapping is because the device spends most of its time at high-voltage and the small on-time limits de-trapping^{(16, 17)}. This gives the corresponding dynamic R_DS(ON) parameter excellent sensitivity to material quality. The increased sensitivity of dynamic R_DS(ON) to detect trapping helps it pick up less electrically active traps. This is consequential because these latent or nascent defects would become more electrically active as they age and later start affecting dynamic R_DS(ON) for operation at regular duty cycles. Dynamic R_DS(ON) under low duty cycle thereby provides an early detection method for the effects of aging. Stable dynamic R_DS(ON) under low duty cycle stress shows that these latent traps are not a concern.

We also evaluated dynamic R_DS(ON) stability under two other modes of operation in power supplies. First is under prolonged off-state conditions by applying off-state stress at a temperature of 125°C and V_DS = 500 V. The dynamic R_DS(ON) is measured in situ every 10 minutes with the results plotted in Figure 3-4, and shows stable behavior with aging. Second is under Dynamic High Temperature Operating Life (DHTOL) operation per JEP180 under both hard and soft-switching operation. The parts had stable efficiency, as described later in section 8, which validates dynamic R_DS(ON) stability. The stable behavior under these conditions further provides assurance that TI GaN technology is natively robust to charge trapping mechanisms.

Figure 3-3 Dynamic R_DS(ON) is stable under low duty-cycle hard-switching best-practice stress conditions. Parts were run at 15–21 kHz with a duty cycle of about 0.5%. The stability demonstrates lack of new trap creation and attests to the excellent material quality. Dynamic R_DS(ON) is measured per JEP173

Figure 3-4 Dynamic R_DS(ON) is stable under off-state high voltage and temperature conditions, providing further assurance that TI GaN is robust to charge trapping mechanisms. The stress was applied using the circuit of Figure 2-1 with I_L = 0 A.

An important difference between GaN and Si FETs is the mechanism causing breakdown. The drain breakdown voltage of Si power FETs is limited by impact ionization, resulting in their voltage rating being limited by avalanche breakdown. As a result, Silicon power FETs do not have much headroom above their voltage rating for transient events. GaN has avalanche⁽¹⁸⁾ capability, but its three-times larger bandgap, allows it to better withstand higher fields without avalanching. The voltage rating of GaN FETs is typically lower than the avalanche limit of the material, giving them transient voltage capability. This aspect allows them to switch through surge without avalanching, as is discussed later.

Finally, it is important to address the effects of current flow at high voltage. Current flows at high voltage during hard-switching in any power device, as explained in reference 5. There are two relevant effects. Firstly, current flow at high voltage creates hot carriers. Their higher energy enables them to scatter into a larger volume, which can result in more charge trapping and cause an increase in dynamic R_DS(ON). Hot carriers can also cause wear out or degradation due to defect generation. Current flow at high voltage can also exercise safe operating area (SOA) boundaries, for which the part needs lifetime reliability. TI GaN is robust to failure modes arising due to hot carriers. As shown in Figure 3-3, we validate long-term dynamic R_DS(ON) stability at stringent low duty-cycle operation under hot-carrier creating hard switching conditions. The hard-switching lifetime and SOA aspects are discussed later.