Methods for Mitigating ADC Memory Cross-Talk

Abstract

High-speed multiplexed analog-to-digital converters (ADCs) like those found on C2000™ series microcontrollers enable fast sensing of multiple feedback signals in real-time control applications. The signal conditioning circuits for these feedback signals should be carefully designed and evaluated to ensure that adequate settling is achieved in the time allocated for the ADC's sample-and-hold (S+H). In cases where adequate settling is not achieved in the hardware design of the signal conditioning circuits, memory cross-talk issues can arise in the system. This application report reviews the causes and symptoms of memory cross-talk and then presents two possible strategies for mitigating the memory cross-talk error: dedicating an ADC to the affected signal (resulting in only self cross-talk) and sampling ground before the affected signal (transforming the memory cross-talk into a gain error, which can subsequently be calibrated out of the system).

Project collateral discussed in this document can be downloaded from the following URL: https://www.ti.com/lit/zip/spracw9.

Trademarks

C2000™ and TINA-TI™ are trademarks of Texas Instruments.

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1 Introduction

Proper design and evaluation of the signal conditioning circuits driving an ADC input is an essential step for ensuring good ADC performance. Of primary concern is the settling performance: can the circuit driving the ADC input charge the ADC's sample-and-hold (S+H) circuit to within acceptable tolerance of the voltage to be sensed in the allocated S+H time? If not, the sensed voltage will have some error. Furthermore, in systems where the ADC is scanning through multiple multiplexed inputs to be sampled (a common use case in real-time control applications), this error will show up as memory cross-talk: the value of the previous conversion in the sampling sequence will effect the results of the signal that was sampled with inadequate S+H settling.

1.1 Memory Cross-Talk Challenges

Due to the nature of the memory cross-talk, the error can appear systematic (if the previous conversion result is correlated to the conversion result experiencing the error) or random (if the previous conversion result is changing asynchronously with respect to the signal experiencing the cross-talk). The error can also appear constant if and when the previously converted channel is not changing very fast.

Because the error can manifest in many different ways, it can be very hard to diagnose in a system. Furthermore, it is difficult to compensate for memory cross talk: oversampling and averaging is not very effective in reducing the magnitude since the error is not fully random, but the error is also usually not systematic enough to be calibrated out of the system as if it were a fixed gain or offset error.