Packaging information
| Package | Pins TSSOP (PW) | 16 |
| Operating temperature range (°C) -55 to 125 |
| Package qty | Carrier 3,000 | LARGE T&R |
Features for the SN74LV595B-EP
- 2 V to 5.5 V V CC operation
- Supports mixed-mode voltage operation on all ports
- I off supports partial-power-down mode operation
- Latch-up performance exceeds 250 mA per JESD 17
- Operating ambient temperature: -55°C to +125°C
- Supports defense, aerospace, and medical applications:
- Controlled baseline
- One assembly and test site
- One fabrication site
- Extended product life cycle
- Product traceability
Description for the SN74LV595B-EP
The SN74LV595B-EP contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear ( SRCLR) input, serial (SER) input, and a serial output for cascading. When the output-enable ( OE) input is high, all outputs except Q H’ are in the high-impedance state.
The device is fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.