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AM5K2E04

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Sitara processor: quad-Arm Cortex-A15

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Errata

AM5K2E04

ACTIVE
Data sheet Order now

Product details

Arm CPU 4 Arm Cortex-A15 Arm (max) (MHz) 1250, 1400 Coprocessors Network co-processor CPU 32-bit Protocols Ethernet Ethernet MAC 8-Port 1Gb switch PCIe 4 PCIe Gen 2 Hardware accelerators Packet Accelerator, Security Accelerator Features Networking Operating system Linux, RTOS Rating Catalog Operating temperature range (°C) -40 to 100
Arm CPU 4 Arm Cortex-A15 Arm (max) (MHz) 1250, 1400 Coprocessors Network co-processor CPU 32-bit Protocols Ethernet Ethernet MAC 8-Port 1Gb switch PCIe 4 PCIe Gen 2 Hardware accelerators Packet Accelerator, Security Accelerator Features Networking Operating system Linux, RTOS Rating Catalog Operating temperature range (°C) -40 to 100
FCBGA (ABD) 1089 729 mm² 27 x 27
  • ARM® Cortex®-A15 MPCore™ CorePac
    • Up to Four ARM Cortex-A15 Processor Cores at
      up to 1.4-GHz
    • 4MB L2 Cache Memory Shared by all Cortex-
      A15 Processor Cores
    • Full Implementation of ARMv7-A Architecture
      Instruction Set
    • 32KB L1 Instruction and Data Caches per Core
    • AMBA 4.0 AXI Coherency Extension (ACE)
      Master Port, Connected to MSMC (Multicore
      Shared Memory Controller) for Low Latency
      Access to SRAM and DDR3
  • Multicore Shared Memory Controller (MSMC)
    • 2 MB SRAM Memory for ARM CorePac
    • Memory Protection Unit for Both SRAM and
      DDR3_EMIF
  • Multicore Navigator
    • 8k Multi-Purpose Hardware Queues with Queue
      Manager
    • One Packet-Based DMA Engine for Zero-
      Overhead Transfers
  • Network Coprocessor
    • Packet Accelerator Enables Support for
      • Transport Plane IPsec, GTP-U, SCTP,
        PDCP
      • L2 User Plane PDCP (RoHC, Air Ciphering)
      • 1 Gbps Wire Speed Throughput at 1.5
        MPackets Per Second
    • Security Accelerator Engine Enables Support for
      • IPSec, SRTP, 3GPP and WiMAX Air
        Interface, and SSL/TLS Security
      • ECB, CBC, CTR, F8, A5/3, CCM, GCM,
        HMAC, CMAC, GMAC, AES, DES, 3DES,
        Kasumi, SNOW 3G, SHA-1, SHA-2 (256-bit
        Hash), MD5
      • Up to 6.4 Gbps IPSec and 3 Gbps Air
        Ciphering
    • Ethernet Subsystem
      • Eight SGMII Ports with Wire Rate Switching
      • IEEE1588 v2 (with Annex D/E/F) Support
      • 8 Gbps Total Ingress/Egress Ethernet BW
        from Core
      • Audio/Video Bridging (802.1Qav/D6.0)
      • QOS Capability
      • DSCP Priority Mapping
  • Peripherals
    • Two PCIe Gen2 Controllers with Support for
      • Two Lanes per Controller
      • Supports Up to 5 GBaud
    • One HyperLink
      • Supports Connections to Other KeyStone Architecture
        Devices Providing Resource
        Scalability
      • Supports Up to 50 GBaud
    • 10-Gigabit Ethernet (10-GbE) Switch Subsystem
      • Two SGMII/XFI Ports with Wire Rate
        Switching and MACSEC Support
      • IEEE1588 v2 (with Annex D/E/F) Support
    • One 72-Bit DDR3/DDR3L Interface with Speeds Up
      to 1600 MTPS in DDR3 Mode
    • EMIF16 Interface
    • Two USB 2.0/3.0 Controllers
    • USIM Interface
    • Two UART Interfaces
    • Three I2C Interfaces
    • 32 GPIO Pins
    • Three SPI Interfaces
    • One TSIP
      • Support 1024 DS0s
      • Support 2 Lanes at 32.768/16.3848.192
        Mbps Per Lane
  • System Resources
    • Three On-Chip PLLs
    • SmartReflex Automatic Voltage Scaling
    • Semaphore Module
    • Twelve 64-Bit Timers
    • Five Enhanced Direct Memory Access (EDMA)
      Modules
  • Commercial Case Temperature:
    • 0°C to 85°C
  • Extended Case Temperature:
    • –40°C to 100°C
  • ARM® Cortex®-A15 MPCore™ CorePac
    • Up to Four ARM Cortex-A15 Processor Cores at
      up to 1.4-GHz
    • 4MB L2 Cache Memory Shared by all Cortex-
      A15 Processor Cores
    • Full Implementation of ARMv7-A Architecture
      Instruction Set
    • 32KB L1 Instruction and Data Caches per Core
    • AMBA 4.0 AXI Coherency Extension (ACE)
      Master Port, Connected to MSMC (Multicore
      Shared Memory Controller) for Low Latency
      Access to SRAM and DDR3
  • Multicore Shared Memory Controller (MSMC)
    • 2 MB SRAM Memory for ARM CorePac
    • Memory Protection Unit for Both SRAM and
      DDR3_EMIF
  • Multicore Navigator
    • 8k Multi-Purpose Hardware Queues with Queue
      Manager
    • One Packet-Based DMA Engine for Zero-
      Overhead Transfers
  • Network Coprocessor
    • Packet Accelerator Enables Support for
      • Transport Plane IPsec, GTP-U, SCTP,
        PDCP
      • L2 User Plane PDCP (RoHC, Air Ciphering)
      • 1 Gbps Wire Speed Throughput at 1.5
        MPackets Per Second
    • Security Accelerator Engine Enables Support for
      • IPSec, SRTP, 3GPP and WiMAX Air
        Interface, and SSL/TLS Security
      • ECB, CBC, CTR, F8, A5/3, CCM, GCM,
        HMAC, CMAC, GMAC, AES, DES, 3DES,
        Kasumi, SNOW 3G, SHA-1, SHA-2 (256-bit
        Hash), MD5
      • Up to 6.4 Gbps IPSec and 3 Gbps Air
        Ciphering
    • Ethernet Subsystem
      • Eight SGMII Ports with Wire Rate Switching
      • IEEE1588 v2 (with Annex D/E/F) Support
      • 8 Gbps Total Ingress/Egress Ethernet BW
        from Core
      • Audio/Video Bridging (802.1Qav/D6.0)
      • QOS Capability
      • DSCP Priority Mapping
  • Peripherals
    • Two PCIe Gen2 Controllers with Support for
      • Two Lanes per Controller
      • Supports Up to 5 GBaud
    • One HyperLink
      • Supports Connections to Other KeyStone Architecture
        Devices Providing Resource
        Scalability
      • Supports Up to 50 GBaud
    • 10-Gigabit Ethernet (10-GbE) Switch Subsystem
      • Two SGMII/XFI Ports with Wire Rate
        Switching and MACSEC Support
      • IEEE1588 v2 (with Annex D/E/F) Support
    • One 72-Bit DDR3/DDR3L Interface with Speeds Up
      to 1600 MTPS in DDR3 Mode
    • EMIF16 Interface
    • Two USB 2.0/3.0 Controllers
    • USIM Interface
    • Two UART Interfaces
    • Three I2C Interfaces
    • 32 GPIO Pins
    • Three SPI Interfaces
    • One TSIP
      • Support 1024 DS0s
      • Support 2 Lanes at 32.768/16.3848.192
        Mbps Per Lane
  • System Resources
    • Three On-Chip PLLs
    • SmartReflex Automatic Voltage Scaling
    • Semaphore Module
    • Twelve 64-Bit Timers
    • Five Enhanced Direct Memory Access (EDMA)
      Modules
  • Commercial Case Temperature:
    • 0°C to 85°C
  • Extended Case Temperature:
    • –40°C to 100°C

The AM5K2E0x is a high performance device based on TI’s KeyStone II Multicore SoC Architecture, incorporating the most performance-optimized Cortex-A15 processor dual-core or quad-core CorePac that can run at a core speed of up to 1.4 GHz. TI’s AM5K2E0x device enables a high performance, power-efficient and easy to use platform for developers of a broad range of applications such as enterprise grade networking end equipment, data center networking, avionics and defense, medical imaging, test and automation.

TI’s KeyStone II Architecture provides a programmable platform integrating various subsystems (for example, ARM CorePac (Cortex-A15 Processor Quad Core CorePac), network processing, and uses a queue-based communication system that allows the device resources to operate efficiently and seamlessly. This unique device architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to high-speed IO, to each operate at maximum efficiency with no blocking or stalling.

The AM5K2E0x KeyStone II device integrates a large amount of on-chip memory. The Cortex-A15 processor cores each have 32KB of L1Data and 32KB of L1 Instruction cache. The up to four Cortex A15 cores in the ARM CorePac share a 4MB L2 Cache. The device also integrates 2MB of Multicore Shared Memory (MSMC) that can be used as a shared L3 SRAM. All L2 and MSMC memories incorporate error detection and error correction. For fast access to external memory, this device includes a 64-bit DDR-3 (72-bit with ECC support) external memory interface (EMIF) running at 1600 MTPS.

The device enables developers to use a variety of development and debugging tools that include GNU GCC, GDB, Open source Linux, Eclipse based debugging environment enabling kernel and user space debugging using a variety of Eclipse plug-ins including TI's industry leading IDE Code Composer Studio.

The AM5K2E0x is a high performance device based on TI’s KeyStone II Multicore SoC Architecture, incorporating the most performance-optimized Cortex-A15 processor dual-core or quad-core CorePac that can run at a core speed of up to 1.4 GHz. TI’s AM5K2E0x device enables a high performance, power-efficient and easy to use platform for developers of a broad range of applications such as enterprise grade networking end equipment, data center networking, avionics and defense, medical imaging, test and automation.

TI’s KeyStone II Architecture provides a programmable platform integrating various subsystems (for example, ARM CorePac (Cortex-A15 Processor Quad Core CorePac), network processing, and uses a queue-based communication system that allows the device resources to operate efficiently and seamlessly. This unique device architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to high-speed IO, to each operate at maximum efficiency with no blocking or stalling.

The AM5K2E0x KeyStone II device integrates a large amount of on-chip memory. The Cortex-A15 processor cores each have 32KB of L1Data and 32KB of L1 Instruction cache. The up to four Cortex A15 cores in the ARM CorePac share a 4MB L2 Cache. The device also integrates 2MB of Multicore Shared Memory (MSMC) that can be used as a shared L3 SRAM. All L2 and MSMC memories incorporate error detection and error correction. For fast access to external memory, this device includes a 64-bit DDR-3 (72-bit with ECC support) external memory interface (EMIF) running at 1600 MTPS.

The device enables developers to use a variety of development and debugging tools that include GNU GCC, GDB, Open source Linux, Eclipse based debugging environment enabling kernel and user space debugging using a variety of Eclipse plug-ins including TI's industry leading IDE Code Composer Studio.
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Technical documentation

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Type Title Date
* Data sheet AM5K2E04/02 Multicore ARM KeyStone II System-on-Chip (SoC) datasheet (Rev. D) 11 Mar 2015
* Errata AM5K2E04/02 KeyStone SoC Silicon Errata (Silicon Rev 1.0) (Rev. B) 20 Aug 2015
White paper Understanding Functional Safety FIT Base Failure Rate Estimates per IEC 62380 and SN 29500 (Rev. A) PDF | HTML 30 Apr 2024
User guide ARM Assembly Language Tools v20.2.0.LTS User's Guide (Rev. Z) PDF | HTML 30 Mar 2023
User guide ARM Optimizing C/C++ Compiler v20.2.0.LTS User's Guide (Rev. W) PDF | HTML 30 Mar 2023
Application note DDR3 Design Requirements for KeyStone Devices (Rev. D) PDF | HTML 07 Jul 2022
Application note Using Arm ROM Bootloader on Keystone II Devices PDF | HTML 04 Jun 2019
User guide ARM Assembly Language Tools v19.6.0.STS User's Guide (Rev. X) 03 Jun 2019
User guide ARM Optimizing C/C++ Compiler v19.6.0.STS User's Guide (Rev. U) 03 Jun 2019
Application note Keystone Multicore Device Family Schematic Checklist PDF | HTML 17 May 2019
Application note KeyStone II DDR3 interface bring-up 07 Mar 2019
User guide ARM Assembly Language Tools v18.12.0.LTS User's Guide (Rev. W) 19 Nov 2018
User guide ARM Optimizing C/C++ Compiler v18.12.0.LTS User's Guide (Rev. T) 19 Nov 2018
User guide How-To and Troubleshooting Guide for PRU-ICSS PROFIBUS 24 Sep 2018
User guide ARM Assembly Language Tools v18.1.0.LTS User's Guide (Rev. U) 16 Jan 2018
User guide ARM Optimizing C/C++ Compiler v18.1.0.LTS User's Guide (Rev. R) 16 Jan 2018
User guide ARM Assembly Language Tools v17.9.0.STS User's Guide (Rev. T) 30 Sep 2017
User guide ARM Optimizing C/C++ Compiler v17.9.0.STS User's Guide (Rev. Q) 30 Sep 2017
User guide KeyStone II Architecture Universal Serial Bus 3.0 (USB 3.0) (Rev. A) 21 Aug 2017
Application note Thermal Design Guide for DSP and Arm Application Processors (Rev. B) 14 Aug 2017
User guide Phase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. I) 26 Jul 2017
User guide ARM Assembly Language Tools v17.6.0.STS User's Guide (Rev. S) 21 Jun 2017
User guide ARM Optimizing C/C++ Compiler v17.6.0.STS User's Guide (Rev. P) 21 Jun 2017
Application note Power Consumption Summary for K2E System-on-Chip (SoC) Device Family 14 Jun 2017
Application note Clocking Spreadsheet for K2E Device Family 26 Jan 2017
User guide Serializer/Deserializer (SerDes) for KeyStone II Devices User Guide (Rev. A) 27 Jul 2016
Application note Power Management of KS2 Device (Rev. C) 15 Jul 2016
User guide ARM Assembly Language Tools v16.9.0.LTS User's Guide (Rev. P) 30 Apr 2016
User guide ARM Optimizing C/C++ Compiler v16.9.0.LTS User's Guide (Rev. M) 30 Apr 2016
Application note Throughput Performance Guide for KeyStone II Devices (Rev. B) 22 Dec 2015
Application note Keystone II DDR3 Debug Guide 16 Oct 2015
User guide Enhanced Direct memory Access 3 (EDMA3) for KeyStone Devices User's Guide (Rev. B) 06 May 2015
User guide Gigabit Ethernet (GbE) Switch SS for K2E & K2L Devices User's Guide (Rev. A) 28 Apr 2015
User guide Multicore Navigator (CPPI) for KeyStone Architecture User's Guide (Rev. H) PDF | HTML 09 Apr 2015
User guide DDR3 Memory Controller for KeyStone II Devices User's Guide (Rev. C) 27 Mar 2015
White paper Save power and costs with TI's K2E on-chip networking features 25 Mar 2015
Application note Keystone II DDR3 Initialization 26 Jan 2015
User guide ARM Assembly Language Tools v5.2 User's Guide (Rev. M) 05 Nov 2014
User guide ARM Optimizing C/C++ Compiler v5.2 User's Guide (Rev. J) 05 Nov 2014
User guide Power Sleep Controller (PSC) for KeyStone Devices User's Guide (Rev. C) 04 Sep 2014
White paper KeyStone™-II-based processors: 10G Ethernet as an optical interface 25 Aug 2014
User guide Packet Accelerator 2 (PA2) for K2E and K2L Devices User's Guide 19 Aug 2014
User guide Security Accelerator 2 (SA2) for K2E and K2L Devices User's Guide 19 Aug 2014
White paper Differentiating AM5K2E02 and AM5K2E04 SoCs from Alternate ARM® Cortex®-A15 Devic 14 Aug 2014
User guide Network Coprocessor (NETCP) for K2E and K2L Devices User's Guide 13 Aug 2014
Application note Hardware Design Guide for KeyStone II Devices 24 Mar 2014
User guide PCI Express (PCIe) for KeyStone Devices User's Guide (Rev. D) 30 Sep 2013
User guide Debug and Trace for KeyStone II Devices User's Guide 26 Jul 2013
User guide ARM Bootloader User Guide for KeyStone II Devices 21 Jul 2013
User guide Memory Protection Unit (MPU) for KeyStone Devices User's Guide (Rev. A) 28 Jun 2013
User guide HyperLink for KeyStone Devices User's Guide (Rev. C) 28 May 2013
User guide 10 Gigabit Ethernet Switch Subsystem User Guide for KeyStone II Devices 08 Feb 2013
User guide Multicore Shared Memory Controller (MSMC) User Guide for KeyStone II Devices 12 Nov 2012
Product overview Industrial Imaging: Applications of the K2H and K2E platforms 09 Nov 2012
Product overview Video Infrastructure - Applications of the K2E, K2H platforms 09 Nov 2012
User guide ARM CorePac User Guide for KeyStone II Devices 31 Oct 2012
Application note Multicore Programming Guide (Rev. B) 29 Aug 2012
User guide Serial Peripheral Interface (SPI) for KeyStone Devices User’s Guide (Rev. A) 30 Mar 2012
User guide Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide (Rev. A) 27 Mar 2012
User guide 64-Bit Timer (Timer64) for KeyStone Devices User's Guide (Rev. A) 22 Mar 2012
Application note PCIe Use Cases for KeyStone Devices 13 Dec 2011
User guide Inter-Integrated Circuit (I2C) for KeyStone Devices User's Guide 02 Sep 2011
User guide External Memory Interface (EMIF16) for KeyStone Devices User's Guide (Rev. A) 24 May 2011
User guide C66x DSP Cache User's Guide 09 Nov 2010
Application note Clocking Design Guide for KeyStone Devices 09 Nov 2010
User guide General-Purpose Input/Output (GPIO) forKeyStone Devices User's Guide 09 Nov 2010
Application note Optimizing Loops on the C66x DSP 09 Nov 2010
User guide Telecom Serial Interface Port (TSIP) for KeyStone Devices User's Guide 09 Nov 2010
User guide Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices UG 09 Nov 2010

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Information included:
  • Fab location
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