GUI for evaluation module (EVM)
CDCM7005-SP
Radiation-hardened-assured (RHA) 3.3-V high-performance clock jitter cleaner and synchronizer
Data sheet
CDCM7005-SP
- High Performance LVPECL and LVCMOS PLL
Clock Synchronizer - Two Reference Clock Inputs (Primary and
Secondary Clock) for Redundancy Support
With Manual or Automatic Selection - Accepts LVCMOS Input Frequencies Up to
200 MHz - VCXO_IN Clock is Synchronized to One of the
Two Reference Clocks - VCXO_IN Frequencies Up to 2 GHz (LVPECL)
- Outputs can be a Combination of LVPECL and
LVCMOS (Up to Five Differential LVPECL
Outputs or Up to 10 LVCMOS Outputs) - Output Frequency is Selectable by x1, /2, /3, /4,
/6, /8, /16 on Each Output
Individually - Efficient Jitter Cleaning from Low PLL Loop
Bandwidth - Low Phase Noise PLL Core
- Programmable Phase Offset (PRI_REF and
SEC_REF to Outputs) - Wide Charge Pump Current Range From
200 µA to 3 mA - Analog and Digital PLL Lock Indication
- Provides VBB Bias Voltage Output for Single-
Ended Input Signals (VCXO_IN) - Frequency Hold Over Mode Improves Fail-Safe
Operation - Power-Up Control Forces LVPECL Outputs to Tri-
State at VCC < 1.5 V - SPI Controllable Device Setting
- 3.3-V Power Supply
- High-Performance 52 Pin Ceramic Quad Flat
Pack (HFG) - Rad-Tolerant : 50 kRad (Si) TID
- QML-V Qualified, SMD 5962-07230
- Military Temperature Range: –55°C to 125°C Tcase
- Engineering Evaluation (/EM) Samples are
Available(1)
The CDCM7005-SP is a high-performance, low phase noise and low skew clock synchronizer that synchronizes a VCXO (voltage controlled crystal oscillator) or VCO (voltage controlled oscillator) frequency to one of the two reference clocks. The programmable pre-divider M and the feedback-dividers N and P give a high flexibility to the frequency ratio of the reference clock to VC(X)O as VC(X)O_IN / PRI_REF = (N × P) / M or VC(X)O_IN / SEC_REF = (N × P) / M.
VC(X)O_IN clock operates up to 2 GHz. Through the selection of external VC(X)O and loop filter components, the PLL loop bandwidth and damping factor can be adjust to meet different system requirements.
The CDCM7005-SP can lock to one of two reference clock inputs (PRI_REF and SEC_REF), supports frequency hold-over mode and fast-frequency-locking for fail-safe and increased system redundancy. The outputs of the CDCM7005-SP are user definable and can be any combination of up to five LVPECL outputs or up to 10 LVCMOS outputs. The LVCMOS outputs are arranged in pairs (Y0A:Y0B, Y1A:Y1B, Ω), so that each pair has the same frequency. But each output can be separately inverted and disabled. The built in synchronization latches ensure that all outputs are synchronized for low output skew.
All device settings, like outputs signaling, divider value, input selection, and many more, are programmable by SPI (3-wire serial peripheral interface). SPI allows individually control of the device settings.
The device operates in a 3.3-V environment and is characterized for operation from –55°C to 125°C (Tcase).
Technical documentation
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View all 11 | Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | CDCM7005-SP 3.3-V High Performance Rad-Tolerant Class V, Clock Synchronizer and Jitter Cleaner datasheet (Rev. G) | PDF | HTML | 03 Dec 2015 |
| * | SMD | CDCM7005-SP SMD 5962-07230 | 08 Jul 2016 | |
| * | Radiation & reliability report | CDCM7005MHFG-V Radiation Test Report | 12 Nov 2014 | |
| Application brief | DLA Approved Optimizations for QML Products (Rev. B) | PDF | HTML | 17 May 2024 | |
| Selection guide | TI Space Products (Rev. J) | 12 Feb 2024 | ||
| More literature | TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. A) | 31 Aug 2023 | ||
| Application note | Heavy Ion Orbital Environment Single-Event Effects Estimations (Rev. A) | PDF | HTML | 17 Nov 2022 | |
| Application note | Single-Event Effects Confidence Interval Calculations (Rev. A) | PDF | HTML | 19 Oct 2022 | |
| E-book | Radiation Handbook for Electronics (Rev. A) | 21 May 2019 | ||
| EVM User's guide | CDCM7005EVM-CVAL Evaluation Module (EVM) User's Guide | 11 Sep 2018 | ||
| Application note | Phase Noise/Phase Jitter Performance of CDCM7005 | 26 Jul 2005 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.
Evaluation board
CDCM7005EVM-CVAL — CDCM7005-SP Evaluation Module
The CDCM7005 is a high-performance, low phase noise and low skew clock synchronizer that synchronizes an on-board voltage controlled crystal oscillator (VC(X)O) frequency to an external reference clock. The device operates up to 2 GHz. The PLL loop bandwidth and damping factor can be adjusted to (...)
User guide: PDF
Design tool
CLOCK-TREE-ARCHITECT — Clock tree architect programming software
Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
Simulation tool
PSPICE-FOR-TI — PSpice® for TI design and simulation tool
PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| CFP (HFG) | 52 | Ultra Librarian |
Ordering & quality
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