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CY74FCT162H501T

OBSOLETE

18-Bit Universal Bus Transceivers with Bus-Hold and 3-State Outputs

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Data sheet
CY74FCT162H501T is no longer in production
This product is no longer in production. New designs should consider an alternate product.
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SN74ALVCH16501 ACTIVE 18-bit universal bus transceiver with 3-state outputs Replacement

CY74FCT162H501T

OBSOLETE
Data sheet Order now

Product details

Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 18 IOL (max) (mA) 64 IOH (max) (mA) -32 Input type TTL-Compatible CMOS Output type 3-State Features Bus-hold, Damping resistors, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Technology family FCT Rating Catalog Operating temperature range (°C) -40 to 85
Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 18 IOL (max) (mA) 64 IOH (max) (mA) -32 Input type TTL-Compatible CMOS Output type 3-State Features Bus-hold, Damping resistors, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Technology family FCT Rating Catalog Operating temperature range (°C) -40 to 85
TSSOP (DGG) 56 113.4 mm² 14 x 8.1
  • Ioff supports partial-power-down mode operation
  • Edge-rate control circuitry for significantly improved noise characteristics
  • Typical output skew < 250 ps
  • ESD > 2000V
  • TSSOP (19.6 mil pitch) and SSOP (25-mil pitch) packages
  • Industrial temperature range of -40°C to +85°C
  • VCC = 5V ± 10%
  • CY74FCT16501T Features:
    • 64 mA sink current, 32 mA source current
    • Typical VOLP (ground bounce) <1.0V at VCC = 5V, TA = 25°C
  • CY74FCT162501T Features:
    • Balanced 24 mA output drivers
    • Reduced system switching noise
    • Typical VOLP (ground bounce) <0.6V at VCC = 5V, TA = 25°C
  • CY74FCT162H501T Features:
    • Bus hold retains last active state
    • Eliminates the need for external pull-up or pull-down resistors
  • Ioff supports partial-power-down mode operation
  • Edge-rate control circuitry for significantly improved noise characteristics
  • Typical output skew < 250 ps
  • ESD > 2000V
  • TSSOP (19.6 mil pitch) and SSOP (25-mil pitch) packages
  • Industrial temperature range of -40°C to +85°C
  • VCC = 5V ± 10%
  • CY74FCT16501T Features:
    • 64 mA sink current, 32 mA source current
    • Typical VOLP (ground bounce) <1.0V at VCC = 5V, TA = 25°C
  • CY74FCT162501T Features:
    • Balanced 24 mA output drivers
    • Reduced system switching noise
    • Typical VOLP (ground bounce) <0.6V at VCC = 5V, TA = 25°C
  • CY74FCT162H501T Features:
    • Bus hold retains last active state
    • Eliminates the need for external pull-up or pull-down resistors

These 18-bit universal bus transceivers can be operated in transparent, latched or clock modes by combining D-type latches and D-type flip-flops. Data flow in each direction is controlled by output enable (OEAB and OEBA\), latch enable (LEAB and LEBA), and clock inputs (CLKAB and CLKBA). For A-to-B data flow, the device operates in transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOWlogic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CLKAB. OEAB performs the output enable function on the B port. Data flow from B-to-A is similar to that of A-to-B and is controlled by OEBA\, LEBA, and CLKBA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The CY74FCT16501T is ideally suited for driving high-capacitance loads and low-impedance backplanes.

The CY74FCT162501T has 24-mA balanced output drivers with current limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162501T is ideal for driving transmission lines.

The CY74FCT162H501T is a 24-mA balanced output part, that has "bus hold" on the data inputs. The device retains the input\x92s last state whenever the input goes to high impedance. This eliminates the need for pull-up/down resistors and prevents floating inputs.

These 18-bit universal bus transceivers can be operated in transparent, latched or clock modes by combining D-type latches and D-type flip-flops. Data flow in each direction is controlled by output enable (OEAB and OEBA\), latch enable (LEAB and LEBA), and clock inputs (CLKAB and CLKBA). For A-to-B data flow, the device operates in transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOWlogic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CLKAB. OEAB performs the output enable function on the B port. Data flow from B-to-A is similar to that of A-to-B and is controlled by OEBA\, LEBA, and CLKBA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The CY74FCT16501T is ideally suited for driving high-capacitance loads and low-impedance backplanes.

The CY74FCT162501T has 24-mA balanced output drivers with current limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162501T is ideal for driving transmission lines.

The CY74FCT162H501T is a 24-mA balanced output part, that has "bus hold" on the data inputs. The device retains the input\x92s last state whenever the input goes to high impedance. This eliminates the need for pull-up/down resistors and prevents floating inputs.
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* Data sheet 18-Bit Registered Transceivers datasheet (Rev. B) 19 Sep 2001

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